Abstract: An interrupt sensitive extract byte instruction scheme is presented herein. The interrupt sensitive extract by instruction extracts bytes from data, depending on the presence of an interrupt. The extract byte instruction extracts bytes from data in the absence of the interrupt and does not extract bytes in the presence of the interrupt. The interrupt can be triggered by a set of counters that count the number of extracted bytes. By loading the counters with a particular number, the interrupt can be generated when the particular number of data bytes is extracted.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Abstract: Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order.

Abstract: An interrupt sensitive extract byte instruction scheme is presented herein. The interrupt sensitive extract by instruction extracts bytes from data, depending on the presence of an interrupt. The extract byte instruction extracts bytes from data in the absence of the interrupt and does not extract bytes in the presence of the interrupt. The interrupt can be triggered by a set of counters that count the number of extracted bytes. By loading the counters with a particular number, the interrupt can be generated when the particular number of data bytes is extracted.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.