Patents by Inventor Manoj M. Mhala
Manoj M. Mhala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11754616Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.Type: GrantFiled: May 27, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj M. Mhala, Calvin Yi-Ping Chao
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Publication number: 20220337206Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
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Patent number: 11424726Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.Type: GrantFiled: April 1, 2020Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
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Publication number: 20210373068Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj M. Mhala, Calvin Yi-Ping Chao
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Publication number: 20210313940Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
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Patent number: 9881949Abstract: A sensing device includes: a sampling circuit arranged to sample a sensing signal for generating a signal in response to a sampling signal having a monotonically increasing waveform; and a conversion circuit arranged to convert the signal into a digital output signal when the signal reaches a predetermined threshold of the conversion circuit.Type: GrantFiled: June 17, 2015Date of Patent: January 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Min Liu, Manoj M. Mhala
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Publication number: 20160370224Abstract: A sensing device includes: a sampling circuit arranged to sample a sensing signal for generating a signal in response to a sampling signal having a monotonically increasing waveform; and a conversion circuit arranged to convert the signal into a digital output signal when the signal reaches a predetermined threshold of the conversion circuit.Type: ApplicationFiled: June 17, 2015Publication date: December 22, 2016Inventors: CHIH-MIN LIU, MANOJ M. MHALA
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Patent number: 8692571Abstract: The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.Type: GrantFiled: July 15, 2011Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fang-Shi Jordan Lai, Chih-Cheng Lu, Yung-Fu Lin, Hsu-Feng Hsueh, Chin-Hao Chang, Cheng Yen Weng, Manoj M. Mhala
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Patent number: 8493259Abstract: A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.Type: GrantFiled: December 6, 2011Date of Patent: July 23, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fang-Shi Jordan Lai, Hsu-Feng Hsueh, Chin-Hao Chang, Cheng Yen Weng, Chih-Cheng Lu, Manoj M. Mhala, Yung-Fu Lin
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Publication number: 20130141260Abstract: A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fang-Shi Jordan LAI, Hsu-Feng HSUEH, Chin-Hao CHANG, Cheng Yen WENG, Chih-Cheng LU, Manoj M. MHALA, Yung-Fu LIN
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Patent number: 8441384Abstract: A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.Type: GrantFiled: February 18, 2011Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang-Shi Lai, Manoj M. Mhala, Yung-Fu Lin, Hsu-Feng Hsueh, Chin-Hao Chang, Cheng Yen Weng
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Patent number: 8416105Abstract: An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.Type: GrantFiled: February 17, 2011Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang-Shi Jordan Lai, Chin-Hao Chang, Manoj M. Mhala, Hsu-Feng Hsueh, Yung-Fu Lin, Cheng Yen Weng
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Publication number: 20130015876Abstract: The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fang-Shi Jordan LAI, Chih-Cheng LU, Yung-Fu LIN, Hsu-Feng HSUEH, Chin-Hao CHANG, Cheng Yen WENG, Manoj M. MHALA
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Patent number: 8279102Abstract: An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier.Type: GrantFiled: October 5, 2010Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fang-Shi Jordan Lai, Hsu-Feng Hsueh, Cheng Yen Weng, Yung-Fu Lin, Manoj M. Mhala, Tao Wen Chung, Chin-Hao Chang
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Publication number: 20120212359Abstract: An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.Type: ApplicationFiled: February 17, 2011Publication date: August 23, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang-Shi Jordan Lai, Chin-Hao Chang, Manoj M. Mhala, Hsu-Feng Hsueh, Yung-Fu Lin, Cheng Yen Weng
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Publication number: 20120212361Abstract: A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.Type: ApplicationFiled: February 18, 2011Publication date: August 23, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang-Shi Lai, Manoj M. Mhala, Yung-Fu Lin, Hsu-Feng Hsueh, Chin-Hao Chang, Cheng Yen Weng
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Patent number: 8228221Abstract: In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled.Type: GrantFiled: September 28, 2010Date of Patent: July 24, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fang-Shi Jordan Lai, Hsu-Feng Hsueh, Cheng Yen Weng, Yung-Fu Lin, Manoj M. Mhala, Tao Wen Chung, Chin-Hao Chang
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Publication number: 20120081244Abstract: An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fang-Shi Jordan LAI, Hsu-Feng HSUEH, Cheng Yen WENG, Yung-Fu LIN, Manoj M. MHALA, Tao Wen CHUNG, Chin-Hao CHANG
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Publication number: 20120075132Abstract: In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fang-Shi Jordan LAI, Hsu-Feng HSUEH, Cheng Yen WENG, Yung-Fu LIN, Manoj M. MHALA, Tao Wen CHUNG, Chin-Hao CHANG