Patents by Inventor Manoj N. Rana

Manoj N. Rana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6727732
    Abstract: A method and a circuit detect the presence of a high-speed signal, such as a high-speed differential signal, based on a software-programmable signal amplitude threshold. In one embodiment, when the amplitude threshold is exceeded, a current is generated to charge a capacitor. The voltage on the capacitor is compared to a second pre-set voltage in a low-speed comparator, which provides an output voltage indicating detection of the high-speed signal.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: April 27, 2004
    Assignee: BitBlitz Communications, Inc.
    Inventors: Bin Wu, Manoj N. Rana
  • Patent number: 6724594
    Abstract: There is disclosed a test multiplexer having over voltage protection for use in integrated circuitry, along with methods of operating the same. An exemplary test multiplexer according to one embodiment of the present invention includes a plurality of MOSFET devices and over voltage protection circuitry. The plurality of MOSFET devices, including both p-type and n-type MOSFET devices, cooperate to pass an input signal to an output signal line of the test multiplexer while the test multiplexer is enabled. The over voltage protection circuitry is biased so that a difference between the input signal voltage and a bias voltage does not exceed breakdown when the test multiplexer is disabled. An important aspect hereof is that the test multiplexer is compliant to input voltages that exceed the positive supply rail, and is capable of sustaining a high or otherwise out of threshold single ended voltage at the input without latching up.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: April 20, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Laurence D. Lewicki, Manoj N. Rana, Arlo Aude
  • Publication number: 20020075618
    Abstract: There is disclosed a test multiplexer having over voltage protection for use in integrated circuitry, along with methods of operating the same. An exemplary test multiplexer according to one embodiment of the present invention includes a plurality of MOSFET devices and over voltage protection circuitry. The plurality of MOSFET devices, including both p-type and n-type MOSFET devices, cooperate to pass an input signal to an output signal line of the test multiplexer while the test multiplexer is enabled. The over voltage protection circuitry is biased so that a difference between the input signal voltage and a bias voltage does not exceed breakdown when the test multiplexer is disabled. An important aspect hereof is that the test multiplexer is compliant to input voltages that exceed the positive supply rail, and is capable of sustaining a high or otherwise out of threshold single ended voltage at the input without latching up.
    Type: Application
    Filed: December 20, 2000
    Publication date: June 20, 2002
    Inventors: Laurence D. Lewicki, Manoj N. Rana, Arlo Aude