Patents by Inventor Manoj R. Sastry
Manoj R. Sastry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940888Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults.Type: GrantFiled: September 14, 2021Date of Patent: March 26, 2024Assignee: INTEL CORPORATIONInventors: Santosh Ghosh, Marcio Juliato, Manoj R. Sastry
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Patent number: 11863991Abstract: A first roadway system receives a communication from a second roadway system over a wireless channel, where the communication includes a description of a physical object within a driving environment. Characteristics of the physical object are determined based on sensors of the first roadway system. The communication is determined to contain an anomaly based on a comparison of the description of the physical object with the characteristics determined based on the sensors of the first roadway system. Misbehavior data is generated to describe the anomaly. A remedial action is initiated based on the anomaly.Type: GrantFiled: December 23, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Liuyang Lily Yang, Manoj R. Sastry, Xiruo Liu, Moreno Ambrosin
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Patent number: 11863569Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.Type: GrantFiled: November 17, 2021Date of Patent: January 2, 2024Assignee: INTEL CORPORATIONInventors: Marcio Rogerio Juliato, Shabbir Ahmed, Santosh Ghosh, Christopher Gutierrez, Manoj R. Sastry
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Publication number: 20230376637Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Applicant: Intel CorporationInventors: Manoj R. Sastry, Alpa Narendra Trivedi, Men Long
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Patent number: 11768964Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.Type: GrantFiled: February 23, 2022Date of Patent: September 26, 2023Assignee: INTEL CORPORATIONInventors: Manoj R. Sastry, Alpa Narendra Trivedi, Men Long
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Publication number: 20230284029Abstract: A first roadway system receives a communication from a second roadway system over a wireless channel, where the communication includes a description of a physical object within a driving environment. Characteristics of the physical object are determined based on sensors of the first roadway system. The communication is determined to contain an anomaly based on a comparison of the description of the physical object with the characteristics determined based on the sensors of the first roadway system. Misbehavior data is generated to describe the anomaly. A remedial action is initiated based on the anomaly.Type: ApplicationFiled: December 23, 2022Publication date: September 7, 2023Applicant: Intel CorporationInventors: Liuyang Lily Yang, Manoj R. Sastry, Xiruo Liu, Moreno Ambrosin
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Patent number: 11700130Abstract: Logic may implement protocols and procedures for vehicle-to-vehicle communications for platooning. Logic may implement a communications topology to distinguish time-critical communications from non-time-critical communications. Logic may sign time-critical communications with a message authentication code (MAC) algorithm with a hash function such as Keccak MAC or a Cipher-based MAC. Logic may generate a MAC based on pairwise, symmetric keys to sign the time-critical communications. Logic may sign non-time-critical communications with a digital signature. Logic may encrypt non-time-critical communications. Logic may append a certificate to non-time-critical communications. Logic may append a header to messages to create data packets and may include a packet type to identify time-critical communications. Logic may decode and verify the time-critical messages with a pairwise symmetric key. And logic may prioritize time-critical communications to meet a specified latency.Type: GrantFiled: August 31, 2020Date of Patent: July 11, 2023Assignee: Tahoe Research, Ltd.Inventors: Mohammed Karmoose, Rafael Misoczki, Liuyang Yang, Xiruo Liu, Moreno Ambrosin, Manoj R. Sastry
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Patent number: 11615716Abstract: One embodiment provides an apparatus. The apparatus includes a lightweight cryptographic engine (LCE), the LCE is optimized and has an associated throughput greater than or equal to a target throughput.Type: GrantFiled: July 9, 2020Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Santosh Ghosh, Li Zhao, Manoj R. Sastry
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Patent number: 11570732Abstract: Systems and methods in which devices synchronize their clocks for purposes of data transmission are described. Particularly, the disclosed systems and methods provide detection and mitigation of interference by malicious (or non-malicious) wireless devices with communication of time synchronized data over wireless networks. Systems and methods are provided where times statistics related to multiple instances of wireless time synchronization are collected and collated. Devices in the system can discipline their internal clocks based on the collated time statistics.Type: GrantFiled: September 25, 2020Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Javier Perez-Ramirez, Mikhail Galeev, Susruth Sudhakaran, Dave Cavalcanti, Manoj R Sastry, Christopher N Gutierrez
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Publication number: 20230018402Abstract: The present disclosure describe methods, apparatuses, storage media, and systems for a device disposed at an edge of a vehicular communication network or vehicles within a coverage area of the device. The device is to generate a list of vehicle security data to be distributed to vehicles currently within a coverage area of the device, based at least in part on a context related to the vehicles. The device is further to announce, on a control channel communicatively coupling the device and the vehicles, that the list of vehicle security data are available and a service channel to receive the list of vehicle security data. The list of vehicle security data are to be provided to the vehicles via the service channel. Other embodiments may be described and claimed.Type: ApplicationFiled: July 14, 2022Publication date: January 19, 2023Inventors: Xiruo Liu, Liuyang Yang, Leonardo Gomes Baltar, Moreno Ambrosin, Manoj R. Sastry
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Patent number: 11553346Abstract: A first roadway system receives a communication from a second roadway system over a wireless channel, where the communication includes a description of a physical object within a driving environment. Characteristics of the physical object are determined based on sensors of the first roadway system. The communication is determined to contain an anomaly based on a comparison of the description of the physical object with the characteristics determined based on the sensors of the first roadway system. Misbehavior data is generated to describe the anomaly. A remedial action is initiated based on the anomaly.Type: GrantFiled: December 27, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Liuyang Lily Yang, Manoj R. Sastry, Xiruo Liu, Moreno Ambrosin
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Publication number: 20220405427Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.Type: ApplicationFiled: February 23, 2022Publication date: December 22, 2022Inventors: Manoj R. Sastry, Alpa Narendra Trivedi, Men Long
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Patent number: 11516012Abstract: In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.Type: GrantFiled: January 8, 2021Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Santosh Ghosh, Andrew H. Reinders, Sudhir K. Satpathy, Manoj R. Sastry
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Patent number: 11445362Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for a device disposed at an edge of a vehicular communication network or vehicles within a coverage area of the device. The device is to generate a list of vehicle security data to be distributed to vehicles currently within a coverage area of the device, based at least in part on a context related to the vehicles. The device is further to announce, on a control channel communicatively coupling the device and the vehicles, that the list of vehicle security data are available and a service channel to receive the list of vehicle security data. The list of vehicle security data are to be provided to the vehicles via the service channel. Other embodiments may be described and claimed.Type: GrantFiled: December 27, 2019Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Xiruo Liu, Liuyang Yang, Leonardo Gomes Baltar, Moreno Ambrosin, Manoj R. Sastry
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Patent number: 11423162Abstract: A vehicle control system, including an in-vehicle bus and a plurality of electronic control units (ECUs) coupled to the in-vehicle bus, wherein at least one ECU of the plurality of ECUs is configured to: receive, at a respective at least one ECU of the plurality of ECUs, a message in a message stream on the in-vehicle bus; evaluate the message to determine at least one of a confidence value of the security classification, a significance value of the message, or a bounds check value of the message; and determine in real-time to allow or deny the message to the vehicle control system based on at least one of the significance value of the message, the bounds check value of the message, or the confidence value of the security classification of the message, to provide a sanitized message stream to the vehicle control system.Type: GrantFiled: March 27, 2020Date of Patent: August 23, 2022Assignee: INTEL CORPORATIONInventors: Marcio Juliato, Shabbir Ahmed, Maria Soledad Elli, Christopher Noe Gutierrez, Vuk Lesi, Manoj R. Sastry, John Charles Weast, Liuyang Lily Yang
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Publication number: 20220240168Abstract: A computing node to implement a management entity in a CP-based network. The node including processing circuitry configured to encode an inquiry message requesting information on CPS capabilities. Response messages are received from a set of sensing nodes of a plurality of sensing nodes in response to the inquiry message. The response messages include the information on the CPS capabilities of the set of sensing nodes. A notification message indicating selecting of a sensing node as a sensing coordinator is encoded for transmission. Sensed data received in a broadcast message from the sensing coordinator is decoded. The sensed data including data associated with one or more non-V2X capable sensing nodes.Type: ApplicationFiled: September 23, 2021Publication date: July 28, 2022Inventors: Vallabhajosyula S. Somayazulu, Rath Vannithamby, Kathiravetpillai Sivanesan, Markus Dominik Mueck, Leonardo Gomes Baltar, Marcio Rogerio Juliato, Liuyang Lily Yang, Manoj R. Sastry, Shabbir Ahmed, Christopher Gutierrez, Vuk Lesi, Qian Wang
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Publication number: 20220225227Abstract: System and techniques for network slice resiliency are described herein. An indication of a fault-attack-failure-outage (FAFO) event for a network slice may be received. Here, the network slice is one of multiple network slices. A capacity in a slice segment may be estimated to determine whether there is enough capacity to meet a service level agreement (SLA) of the multiple network slices based on the FAFO event. In this case, the slice segment is a set of physical resources shared by the multiple network slices. Operation of the slice segment may then be modified based on results from estimating the capacity in the slice segment to address impacts from the FAFO event.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Satish Chandra Jha, S M Iftekharul Alam, Vesh Raj Sharma Banjade, Ned M. Smith, Arvind Merwaday, Kshitij Arun Doshi, Francesc Guim Bernat, Liuyang Lily Yang, Kuilin Clark Chen, Christian Maciocco, Marcio Rogerio Juliato, Maruti Gupta Hyde, Manoj R. Sastry
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Publication number: 20220083439Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults.Type: ApplicationFiled: September 14, 2021Publication date: March 17, 2022Inventors: Santosh Ghosh, Marcio Juliato, Manoj R. Sastry
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Publication number: 20220078201Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Marcio Rogerio Juliato, Shabbir AHMED, Santosh GHOSH, Christopher GUTIERREZ, Manoj R. Sastry
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Patent number: 11271965Abstract: One embodiment provides an electronic control unit (ECU) for a vehicle. The ECU includes transceiver circuitry, voltage measurement circuitry and feature set circuitry. The transceiver circuitry is to at least one of send and/or receive a message. The voltage measurement circuitry is to determine at least one of a high bus line voltage (VCANH) value and/or a low bus line voltage (VCANL) value, for each zero bit of at least one zero bit of a received message. The received the message includes a plurality of bits. The feature set circuitry is to determine a value of at least one feature of a feature set based, at least in part, on at least one of a high acknowledge (ACK) threshold voltage (VthH) and/or a low ACK threshold voltage (VthL). The feature set includes at least one of an operating most frequently measured VCANH value (VfreqH2) of a number of VCANH values and/or an operating most frequently measured VCANL value (VfreqL2) of a number of VCANL values.Type: GrantFiled: March 3, 2020Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Kyong-Tak Cho, Li Zhao, Manoj R. Sastry