Patents by Inventor Manoj Shenoy

Manoj Shenoy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118376
    Abstract: Technology for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. The memory system determines one or more read parameters for the selected tier based on the programmed/erased states of the other tiers in the block. For example, the memory system may select read reference levels for the selected tier based on the programmed/erased states of the other tiers. In an aspect, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES).
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Manoj Shenoy, Gopu S, Binoy Jose Panakkal