Abstract: An example embodiment may involve estimating, from genetic data of a plurality of individuals, identity-by-descent (IBD) segments; forming, from the IBD segments, a relationship graph representing genetic linkages between the individuals; determining, by applying a stochastic block model to the relationship graph, a plurality of genetic groups, wherein each of the genetic groups is assigned a respective subset of the individuals who share a greater amount of IBD segment length with one another than with a further respective subset of the individuals who are in other of the genetic groups; and training, for each of the genetic groups, a respective classifier based on (i) input including genome-wide local ancestry proportions of the individuals and sums of IBD segments for the individuals in the respective genetic group, and (ii) associated output of assignments of the individuals to the genetic groups.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: A multipurpose computer accessory having a flat base, an under-cushion, and means for connecting any one or more of a keyboard, mouse, touchpad, scroll ball, camera, loudspeaker, USB port, portable device docking station component, video display, or hard drive to an external device such as a laptop or desktop computer.

Abstract: A laptop docking apparatus having a base and lap rest. The base has an internal duct and fan for venting heat away from the underside of the laptop as well as an accessory bay for removable hard drives or the like, as well as a removable battery to power the device and the laptop. The laptop rest is connectable to the base and has a keyboard, mouse, and internal speakers.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system made up of a temperature sensor which includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal of the first delay stage, and generates a delayed output signal from the output of the first delay stage. The first delay stage and the second delay stage are coupled a voltage supply. The magnitude of the delay of the second delayed signal is inversely proportional to the magnitude of the supply voltage to substantially the same degree that the delayed output signal of the first delay stage is proportional to the magnitude of the supply voltage.

Abstract: A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal of the first delay stage, and generates a delayed output signal from the output of the first delay stage. The first delay stage and the second delay stage are coupled a voltage supply. The magnitude of the delay of the second delayed signal is inversely proportional to the magnitude of the supply voltage to substantially the same degree that the delayed output signal of the first delay stage is proportional to the magnitude of the supply voltage.

Abstract: A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal of the first delay stage, and generates a delayed output signal from the output of the first delay stage. The first delay stage and the second delay stage are coupled a voltage supply. The magnitude of the delay of the second delayed signal is inversely proportional to the magnitude of the supply voltage to substantially the same degree that the delayed output signal of the first delay stage is proportional to the magnitude of the supply voltage.

Abstract: A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal of the first delay stage, and generates a delayed output signal from the output of the first delay stage. The first delay stage and the second delay stage are coupled a voltage supply. The magnitude of the delay of the second delayed signal is inversely proportional to the magnitude of the supply voltage to substantially the same degree that the delayed output signal of the first delay stage is proportional to the magnitude of the supply voltage.

Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system comprising a temperature sensor comprising a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Abstract: A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for increased leakage at higher temperatures and more closely tailor the timing of the refresh operations to the conditions of the dynamic memory device.

Abstract: A temperature sensor is comprised of a device adapted to provide a first signal having a parameter responsive to temperature. A generator provides a reference signal having a parameter that is substantially consistent over a preselected temperature range. A comparator is electrically coupled to the device and the generator and is adapted to provide a second signal in response to the parameter of the first signal differing from the parameter of the reference signal. A digital filter is coupled to the comparator and is adapted to provide a third signal in response to receiving the second signal for a preselected duration of time.

Abstract: A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for increased leakage at higher temperatures and more closely tailor the timing of the refresh operations to the conditions of the dynamic memory device.

Abstract: A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port.

Abstract: A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port.