Abstract: A method and system for managing command fetches by an Non-Volatile Memory express (NVMe) controller from a plurality of queues in a host maintains a predefined ratio of data throughput, based on the command fetches, between the plurality of queues. Each of the plurality of queues is assigned with a particular priority and weight.

Abstract: Memory management in a multi-core solid state drive (SSD) includes distributing, by a memory access management system, multiple direct memory access (DMA) descriptors that describe a mechanism to access a local memory of each processor among multiple processors in the multi-core solid state drive. A direct memory access engine is configured with logical addresses corresponding to locations described by the direct memory access descriptors in the local memory of each processor. The logical addresses emulate a continuous memory.

Abstract: Method, system, apparatus, and/or non-transitory computer readable medium for customizing data access permission in a data storage system. The system allows for the defining of data access permissions at a function level such that different functions in a host can have different data access permissions, for particular data stored in a storage device of the system.

Abstract: A method for handling namespace reservations in a Non Volatile Memory express (NVMe) controller includes a NVMe hardware module collecting a data access request from a host device, the NVMe hardware module determining a validity of the collected data access request, wherein the validity of the data access request is determined based a reservation specific to the host and data indicated in the data access request, and the NVMe hardware module notifying the NVMe firmware module of the determined validity of the collected data access request. The method further includes a NVMe firmware module accepting the data access request when the data request is notified by the NVMe hardware module as being valid, and the NVMe firmware module rejecting the data access request when the data request is notified by the NVMe hardware module as being invalid.