Abstract: Aspects of the subject disclosure may include, for example, a device including a phase rotator configured to receive a read clock, a flip flop configured to obtain an incoming data stream, and a controller. The controller may be configured to control the phase rotator to perform phase rotation of the read clock based on information-carrying level transitions in the incoming data stream, cause a gapped read clock and an inversion of the gapped read clock to be derived in accordance with the phase rotation, where the gapped read clock being derived via gapping operations associated with the read clock, and output clock selection signals that enable the flip flop to selectively sample the incoming data stream using the gapped read clock and the inversion, thereby facilitating a data handoff between asynchronous clock domains. Other embodiments are disclosed.

Abstract: A coherent optical modem includes an optical interface; and circuitry connected to the optical interface and configured to detect a first timing reference point in a transmit Digital Signal Processor (DSP) frame in a transmit direction from a first node to a second node, and detect a second timing reference point in a receive DSP frame in a receive direction from the second node to the first node, wherein the first timing reference point and the second timing reference point are determined based on a pattern in any DSP frame field including i) padding area, ii) a reserved area, and iii) a DSP Multi-Frame Alignment Signal (MFAS) area. The pattern can be input in select DSP frames for a time period that is greater than a time period for each DSP frame.

Abstract: A coherent optical modem includes an optical interface; and circuitry connected to the optical interface and configured to detect a first timing reference point in a transmit Digital Signal Processor (DSP) frame in a transmit direction from a first node to a second node, and detect a second timing reference point in a receive DSP frame in a receive direction from the second node to the first node, wherein the first timing reference point and the second timing reference point are determined based on a pattern in any DSP frame field including i) padding area, ii) a reserved area, and iii) a DSP Multi-Frame Alignment Signal (MFAS) area. The pattern can be input in select DSP frames for a time period that is greater than a time period for each DSP frame.

Abstract: Systems and methods for estimating a transmit symbol sequence implemented in a coherent receiver include receiving a nominally error-free information bit sequence subsequent to Forward Error Correction (FEC) decoding; determining a nominally error-free estimate of the transmitted bit sequence based on the nominally error-free information bit sequence; and determining a nominally error-free estimate of the transmit symbol sequence by mapping the transmit bit sequence to transmit symbols. The system and methods can further include comparing a transmit optical field based on the transmit symbols to a received optical field for one or more measurements.

Abstract: Systems and methods for estimating a transmit symbol sequence implemented in a coherent receiver include receiving a nominally error-free information bit sequence subsequent to Forward Error Correction (FEC) decoding; determining a nominally error-free estimate of the transmitted bit sequence based on the nominally error-free information bit sequence; and determining a nominally error-free estimate of the transmit symbol sequence by mapping the transmit bit sequence to transmit symbols. The system and methods can further include comparing a transmit optical field based on the transmit symbols to a received optical field for one or more measurements.

Abstract: A network interface includes at least one physical memory, at least one client port, at least one processor accessing the at least one physical memory, and at least one network port. The client port receives data blocks which contain a quantity of bits from at least one first client computer system. The processor temporarily stores the data blocks in the at least one physical memory. The processor interacts with the physical memory and compresses the data blocks to reduce the quantity of bits. The processor further interacts with the physical memory such that the compressed data blocks are encrypted to produce encrypted frames. The at least one network port transmits the encrypted frames across a communication network.

Abstract: In a decoder implementing a belief propagation algorithm for iteratively decoding a Low Density Parity Check (LDPC) encoded data block, a method of computing messages to be sent by a first node of the decoder to at least one neighbor node of the decoder. The method comprises: processing messages received by the first node to remove an echo of a previous message sent by the first node to the at least one neighbor node in a previous iteration, to yield corresponding modified messages; computing a message for a current iteration using the modified messages; and broadcasting the computed message for the current iteration to each of the at least one neighbor nodes.

Abstract: In a decoder implementing a belief propagation algorithm for iteratively decoding a Low Density Parity Check (LDPC) encoded data block, a method of computing messages to be sent by a first node of the decoder to at least one neighbour node of the decoder. The method comprises: processing messages received by the first node to remove an echo of a previous message sent by the first node to the at least one neighbour node in a previous iteration, to yield corresponding modified messages; computing a message for a current iteration using the modified messages; and broadcasting the computed message for the current iteration to each of the at least one neighbour nodes.

Abstract: A network interface includes at least one physical memory, at least one client port, at least one processor accessing the at least one physical memory, and at least one network port. The client port receives data blocks which contain a quantity of bits from at least one first client computer system. The processor temporarily stores the data blocks in the at least one physical memory. The processor interacts with the physical memory and compresses the data blocks to reduce the quantity of bits. The processor further interacts with the physical memory such that the compressed data blocks are encrypted to produce encrypted frames. The at least one network port transmits the encrypted frames across a communication network.

Abstract: A synchronizer/de-synchronizer maps continuous format signals of an arbitrary rate into frames of pre-selected single common rate, such as SONET frames, with no bits changed and very little jitter or wander added. In this way, the continuous format signal may be carried transparently as a tributary of a SONET network. Each frame comprises a definite number of fixed stuff bits, including transport overhead bits and reminder fixed stuff bits. A frame also comprises an adjustable number of adaptive stuff bits, resulting from the phase difference between the arbitrary rate and the common rate. A mapping function is performed in a tributary unit shelf of a SONET transport shelf, and the reverse mapping function is performed in a similar way at the far end of a SONET connection. The stuff bits are spread uniformly within the frame.

Abstract: A synchronizer/de-synchronizer maps continuous format signals of an arbitrary rate into frames of pre-selected single common rate, such as SONET frames, with no bits changed and very little jitter or wander added. In this way, the continuous format signal may be carried transparently as a tributary of a SONET network. Each frame comprises a definite number of fixed stuff bits, including transport overhead bits and reminder fixed stuff bits. A frame also comprises an adjustable number of adaptive stuff bits, resulting from the phase difference between the arbitrary rate and the common rate. A mapping function is performed in a tributary unit shelf of a SONET transport shelf, and the reverse mapping function is performed in a similar way at the far end of a SONET connection. The stuff bits are spread uniformly within the frame.