Patents by Inventor Manolis Katevenis

Manolis Katevenis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5774653
    Abstract: The invention relates to a pipeline buffer for simultaneously transferring N words at each of a succession of clock cycles (CK), comprising N one-word side memories (M0-M3) successively connected such that successive memories each are accessed with one clock cycle delay. The N memories are subjected to the same read or write cycles by control circuitry.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: June 30, 1998
    Assignee: Foundation of Research and Technology-Hellas
    Inventor: Manolis Katevenis