Patents by Inventor Manolito Catalasan

Manolito Catalasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9699000
    Abstract: Aspects of a method and system for utilizing a 10/100/1 G/10 GBase-T PHY device for single channel and shared channel networks are provided. In this regard, at least one switching element may be utilized to configure an Ethernet over twisted pair PHY device for communication over a single and/or shared channel. The switching element may enable switching between a transmitter being coupled to a shared channel and a receiver being coupled to a shared channel. Additionally, the switching elements may be based on whether the transmitter is connected to a standard 10/100/1 G/10 GBase-T network, or to a single and/or shared channel network, for example. In this manner, the configured PHY device may remain compatible with existing Ethernet networks. The PHY device may be configured externally and/or internally. The polarity of transmitted and/or received data may be configured based on a polarity of data received from a shared channel.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: July 4, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Scott Powell, Mark Berman, Joseph Laurence Cordaro, Manolito Catalasan
  • Publication number: 20150172074
    Abstract: Aspects of a method and system for utilizing a 10/100/1 G/10 GBase-T PHY device for single channel and shared channel networks are provided. In this regard, at least one switching element may be utilized to configure an Ethernet over twisted pair PHY device for communication over a single and/or shared channel. The switching element may enable switching between a transmitter being coupled to a shared channel and a receiver being coupled to a shared channel. Additionally, the switching elements may be based on whether the transmitter is connected to a standard 10/100/1 G/10 GBase-T network, or to a single and/or shared channel network, for example. In this manner, the configured PHY device may remain compatible with existing Ethernet networks. The PHY device may be configured externally and/or internally. The polarity of transmitted and/or received data may be configured based on a polarity of data received from a shared channel.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 18, 2015
    Applicant: BROADCOM CORPORATION
    Inventors: Scott POWELL, Mark BERMAN, Joseph Laurence CORDARO, Manolito CATALASAN
  • Patent number: 9001822
    Abstract: Aspects of a method and system for utilizing a 10/100/1G/10GBase-T PHY device for single channel and shared channel networks are provided. In this regard, at least one switching element may be utilized to configure an Ethernet over twisted pair PHY device for communication over a single and/or shared channel. The switching element may enable switching between a transmitter being coupled to a shared channel and a receiver being coupled to a shared channel. Additionally, the switching elements may be based on whether the transmitter is connected to a standard 10/100/1G/10GBase-T network, or to a single and/or shared channel network, for example. In this manner, the configured PHY device may remain compatible with existing Ethernet networks. The PHY device may be configured externally and/or internally. The polarity of transmitted and/or received data may be configured based on a polarity of data received from a shared channel.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Scott Powell, Mark Berman, Joseph Laurence Cordaro, Manolito Catalasan
  • Publication number: 20130182717
    Abstract: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.
    Type: Application
    Filed: November 1, 2012
    Publication date: July 18, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Mark Berman, Manolito Catalasan, Ovidiu Bajdechi, Christopher M. Ward, Bruce H. Conway, Derek Tam, Frank van der Goes
  • Patent number: 8325756
    Abstract: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: December 4, 2012
    Assignee: Broadcom Corporation
    Inventors: Mark Berman, Manolito Catalasan, Ovidiu Bajdechi, Christopher M. Ward, Bruce H. Conway, Derek Tam, Frank Van Der Goes
  • Publication number: 20120127892
    Abstract: Aspects of a method and system for utilizing a 10/100/1 G/10 GBase-T PHY device for single channel and shared channel networks are provided. In this regard, at least one switching element may be utilized to configure an Ethernet over twisted pair PHY device for communication over a single and/or shared channel. The switching element may enable switching between a transmitter being coupled to a shared channel and a receiver being coupled to a shared channel. Additionally, the switching elements may be based on whether the transmitter is connected to a standard 10/100/1 G/10 GBase-T network, or to a single and/or shared channel network, for example. In this manner, the configured PHY device may remain compatible with existing Ethernet networks. The PHY device may be configured externally and/or internally. The polarity of transmitted and/or received data may be configured based on a polarity of data received from a shared channel.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 24, 2012
    Inventors: Scott Powell, Mark Berman, Joseph Laurence Cordaro, Manolito Catalasan
  • Patent number: 8081625
    Abstract: Aspects of a method and system for utilizing a 10/100/1G/10GBase-T PHY device for single channel and shared channel networks are provided. In this regard, at least one switching element may be utilized to configure an Ethernet over twisted pair PHY device for communication over a single and/or shared channel. The switching element may enable switching between a transmitter being coupled to a shared channel and a receiver being coupled to a shared channel. Additionally, the switching elements may be based on whether the transmitter is connected to a standard 10/100/1G/10GBase-T network, or to a single and/or shared channel network, for example. In this manner, the configured PHY device may remain compatible with existing Ethernet networks. The PHY device may be configured externally and/or internally. The polarity of transmitted and/or received data may be configured based on a polarity of data received from a shared channel.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: December 20, 2011
    Assignee: Broadcom Corporation
    Inventors: Scott Powell, Mark Berman, Joseph Laurence Cordaro, Manolito Catalasan
  • Publication number: 20080253356
    Abstract: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Inventors: Mark Berman, Manolito Catalasan, Ovidiu Bajdechi, Christopher M. Ward, Bruce H. Conway, Derek Tam, Frank van der Goes
  • Publication number: 20080186996
    Abstract: Aspects of a method and system for utilizing a 10/100/1G/10GBase-T PHY device for single channel and shared channel networks are provided. In this regard, at least one switching element may be utilized to configure an Ethernet over twisted pair PHY device for communication over a single and/or shared channel. The switching element may enable switching between a transmitter being coupled to a shared channel and a receiver being coupled to a shared channel. Additionally, the switching elements may be based on whether the transmitter is connected to a standard 10/100/1G/10GBase-T network, or to a single and/or shared channel network, for example. In this manner, the configured PHY device may remain compatible with existing Ethernet networks. The PHY device may be configured externally and/or internally. The polarity of transmitted and/or received data may be configured based on a polarity of data received from a shared channel.
    Type: Application
    Filed: September 7, 2007
    Publication date: August 7, 2008
    Inventors: Scott Powell, Mark Berman, Joseph Laurence Cordaro, Manolito Catalasan
  • Publication number: 20080013457
    Abstract: A programmable channel-swap crossbar switch for swapping signal flow from one channel to another within an Ethernet physical layer device (PHY) is presented. The crossbar switch includes two or more programmed multiplexers, each multiplexer configured to receive two or more input signals and to select which one of the input signals to pass to a programmed corresponding channel, such that a first input signal associated with a first channel can be swapped to a second channel as operating conditions necessitate. The crossbar switch can be used for Ethernet communications with various communication speeds, such as 10BaseT, 100BaseT, and Gigabit communications. A crossbar switch can be used in both a transmit path and a receive path. Two crossbar switches may be used in a receive path in order to undo channel swapping for control signal processing. A method of channel-swapping in an Ethernet PHY communications system is also presented.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 17, 2008
    Applicant: Broadcom Corporation
    Inventors: Mark Berman, Manolito Catalasan, Bruce Conway, Kevin Chan
  • Publication number: 20070131966
    Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.
    Type: Application
    Filed: February 2, 2007
    Publication date: June 14, 2007
    Applicant: Broadcom Corporation
    Inventors: Manolito Catalasan, Vafa Rakshani, Edmund Spittles, Tim Sippel, Richard Unda
  • Publication number: 20060022681
    Abstract: A system for detecting connector compatibility with a time domain reflectometry (TDR) circuit on a peripheral device. A cable connects the peripheral device and a second peripheral device. A first connector is for mating to a second connector on the second peripheral device. The time domain reflectometry can be used to detect electrical compatibility of the first and second connectors. The first connector can be an RJ11 connector. The second connector can be an RJ45 connector. The first connector can be a plug, and the second connector can be a socket. The number of pins of the first and second connectors can be different. The first connector can be a telco connector, and the second connector can be an Ethernet connector. The TDR circuit can be part of the peripheral device diagnostics.
    Type: Application
    Filed: August 2, 2004
    Publication date: February 2, 2006
    Applicant: Broadcom Corporation
    Inventors: James Muth, Peiqing Wang, Manolito Catalasan
  • Publication number: 20050242356
    Abstract: Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device.
    Type: Application
    Filed: November 15, 2004
    Publication date: November 3, 2005
    Inventor: Manolito Catalasan