Abstract: Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described.

Abstract: Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described.

Abstract: Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame that has been folded to create folded leads that form a customized array of land pads and vias. The lead frame contains both longer folded lead and shorter folded leads. The longer leads can be folded so that an upper part of the longer leads form vias, the lower part forms part of a land pad array, and a substantially flat part that is connected to a first die containing an IC. The shorter leads can be folded so that a lower part forms part of a land pad array and the short leads are connected to a second die containing in IC. The folded leads can be routed according to the requirements of each specific IC die to which they are connected and therefore can support multiple dies in the semiconductor package. Other embodiments are also described.

Abstract: Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described.

Abstract: Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.

Abstract: Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.

Abstract: Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described.

Abstract: Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described.

Abstract: Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described.

Abstract: Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame that has been folded to create folded leads that form a customized array of land pads and vias. The lead frame contains both longer folded lead and shorter folded leads. The longer leads can be folded so that an upper part of the longer leads form vias, the lower part forms part of a land pad array, and a substantially flat part that is connected to a first die containing an IC. The shorter leads can be folded so that a lower part forms part of a land pad array and the short leads are connected to a second die containing in IC. The folded leads can be routed according to the requirements of each specific IC die to which they are connected and therefore can support multiple dies in the semiconductor package. Other embodiments are also described.

Abstract: Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame with a customized array of lands at the bottom of the package. The lands are connected to a series of leads that are located within the perimeter of the lands. The leads can be routed according to the requirements of each specific IC die which they support and therefore can support both a single die and multiple die in the semiconductor package. Such a configuration provides a flexible routing for optimized layout, a maximized package density, and a higher input/output capability with a smaller package size. Other embodiments are also described.

Abstract: Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.

Abstract: Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.

Abstract: Semiconductor packages that contain multiple dies containing discrete devices and methods for making such devices are described. The semiconductor package contains both a first die containing transistor and second die containing a diode. The interconnect lead of the semiconductor package is connected to the bond pad of the transistor. At the same time, the interconnect lead contains a die attach pad for the diode. The result of this configuration is an integrated functional semiconductor device with a diminished footprint and decreased cost of manufacture. By using more than a single die containing a discrete device in a single semiconductor package, the device can also provide a wider variety of functions. Other embodiments are also described.

Abstract: Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The packages also contain multiple chips that are stacked vertically. The chips are connected through stud bumps, printed interconnect structures, and conductive pillars formed with the package. The packages also contain two different moldings layers that together operate as an encapsulation material. The semiconductor packages contain a full land pad array at both the bottom and the top of the package, allowing the packages to be used in a package-on-package configuration. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.

Abstract: Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described.

Abstract: Wafer-level chip scale (WLCSP) semiconductor packages and methods for making and using the same are described. The WLCSP semiconductor packages contain a grid array of land pads rather than solder balls or solder bumps. The land pads can be provided directly on a semiconductor wafer by using a leadframe interconnect structure that has been formed from a leadframe. The land pads can be used to mount the WLCSP to a circuit board. Such a configuration allows the formation of a thinner chip scale semiconductor package using a simpler manufacturing process, thereby reducing costs and improving performance. Other embodiments are described.

Abstract: Leadframe-free semiconductor packages and methods for making and using the same are described. The semiconductor packages contain an interconnect structure comprising an array of land pads. The interconnect structure is formed from and routed using a printable or wirebondable conductive material and is not formed using any etching procedure. A solderable mask covers the interconnect structure except for the land pads. A die containing an integrated circuit device is connected to the interconnect structure by either a wirebonding process or by a flipchip process. The land pad arrays can contain a solder connector, such as a solder ball or bump, that can be used to connect the semiconductor package to a printed circuit board. Other embodiments are described.

Abstract: Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame with a customized array of lands at the bottom of the package. The lands are connected to a series of leads that are located within the perimeter of the lands. The leads can be routed according to the requirements of each specific IC die which they support and therefore can support both a single die and multiple die in the semiconductor package. Such a configuration provides a flexible routing for optimized layout, a maximized package density, and a higher input/output capability with a smaller package size. Other embodiments are also described.

Abstract: Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described.