Abstract: The present invention provides a jitter attenuator that has a phase locked loop (PLL), the PLL having a programmable bandwidth setting. The jitter attenuator also has a first-in/first-out (FIFO) buffer for storing data, a write clock for providing a write pulse to the FIFO, a read clock for providing a read pulse to the FIFO, and a pointer generator for controlling the programmable bandwidth in response to the difference between the frequencies of the write and read clocks.

Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.

Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.

Abstract: A duty cycle control circuit that consumes lower power and smaller silicon area, and is less susceptible to noise or jitter. In one embodiment, the invention includes a divide-by-two circuit that is edge triggered and generates a signal at its output with half the frequency of the input signal but with a 50% duty cycle. The divide-by-two circuit is followed by a frequency restore circuit that restores the original frequency of the input signal but with its duty cycle regulated at about 50%, or any other desired level.