Abstract: Disclosed is a method and apparatus for accomplishing high speed multiplication of binary numbers using a single clock cycle to achieve the same computational power provided by the multiple clock cycle shift register configurations or the asynchronous multistate logic configurations of the prior art. “Virtual shifts” are achieved by allocating one or more positions, within a register storing the partial products, as place holders, typically zeroes. These place holders can be inserted in a single clock cycle and do not require the multi-staged shift register configurations of the prior art.