Abstract: The invention relates to systems and method to facilitate downloading a data file. In one embodiment, a method includes receiving at a first wireless communication device a request to download a requested data file. A determination is made at the first wireless communication device whether the requested data file is stored at a second wireless communication device with which the first wireless communication device communicates via a local wireless link. If the requested data file is determined to be stored at the second wireless communication device, the first wireless communication device retrieving the requested data file from second wireless communication device via the local wireless link.

Abstract: The invention relates to systems and method to facilitate downloading a data file. In one embodiment, a method includes receiving at a first wireless communication device a request to download a requested data file. A determination is made at the first wireless communication device whether the requested data file is stored at a second wireless communication device with which the first wireless communication device communicates via a local wireless link. If the requested data file is determined to be stored at the second wireless communication device, the first wireless communication device retrieving the requested data file from second wireless communication device via the local wireless link.

Abstract: A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

Abstract: A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

Abstract: An electronic device for transferring data between a serial port and a memory of a CPU is provided having a plurality of data registers for transferring data between said serial port and said memory in response to a first set of control signals, a data bus connected to said registers and said memory for passing data to and from said memory in response to a portion of said first set of control signals, first control circuitry for generating said first set of control signals and for generating at least one interrupt to said CPU, at least one control register connected to said first control circuitry for providing mode control information to said first control circuitry, a plurality of address registers for storing data address, at least one address generator connected to said address registers for automatically generating addresses in response to a second set of control signals, an address bus connected to said address registers, and second control circuitry connected to said address generator, a portion of sai