Abstract: A multi-mode pulse width modulation (PWM) controller for a buck switching regulator includes a multi-mode PWM control circuit where the PWM control circuit is configured to operate in one of multiple control schemes selectable by a mode select signal. In one embodiment, the multi-mode PWM control circuit incorporates a peak current mode control scheme, a voltage mode control scheme, and a valley current mode control scheme. In another embodiment, the multi-mode PWM control circuit further incorporates a constant ON-time control scheme.

Abstract: A multi-phase power block for a switching regulator includes a phase control circuit, N power cells and a current sharing control circuit. The phase control circuit is configured to receive a single phase PWM clock signal and generate N clock signals in N phases. Each of the N power cells includes a pair of power switches, gate drivers, a control circuit receiving one of the N clock signals and generating gate drive signals for the gate drivers, and an inductor. The current sharing control circuit is configured to assess the inductor current at the inductor of the N power cells and to generate duty cycle control signals for the N power cells. The duty cycle control signals are applied to the control circuits to adjust the duty cycle of one or more clock signals supplied to the power cells to balance a current loading among the N power cells.

Abstract: A multi-mode pulse width modulation (PWM) controller for a buck switching regulator includes a multi-mode PWM control circuit where the PWM control circuit is configured to operate in one of multiple control schemes selectable by a mode select signal. In one embodiment, the multi-mode PWM control circuit incorporates a peak current mode control scheme, a voltage mode control scheme, and a valley current mode control scheme. In another embodiment, the multi-mode PWM control circuit further incorporates a constant ON-time control scheme.

Abstract: A multi-phase power block for a switching regulator includes a phase control circuit, N power cells and a current sharing control circuit. The phase control circuit is configured to receive a single phase PWM clock signal and generate N clock signals in N phases. Each of the N power cells includes a pair of power switches, gate drivers, a control circuit receiving one of the N clock signals and generating gate drive signals for the gate drivers, and an inductor. The current sharing control circuit is configured to assess the inductor current at the inductor of the N power cells and to generate duty cycle control signals for the N power cells. The duty cycle control signals are applied to the control circuits to adjust the duty cycle of one or more clock signals supplied to the power cells to balance a current loading among the N power cells.

Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.

Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.

Abstract: The present invention has various aspects relating to the maximization of current carrying capacity of wafer level packaged chip scale solder pad mounted integrated circuits. In one aspect, the solder pad areas are maximized by using rectangular solder pads spaced as close together as reliable mounting to a circuit board will allow. In another aspect, multiple contact pads may be used for increasing the current capacity without using contact pads of different areas. In still another aspect, vias are used to directly connect one lead of high current component or components to a contact pad directly above that component, and to route a second lead of the high current component to an adjacent contact pad by way of a thick metal interconnect layer.

Abstract: The present invention provides an improved method and apparatus to measure p-n junction device temperature by testing a device with M-Levels of applied collector current, sensing changes in output characteristics, and calculating the device current offset error and leakage current error due to parasitic parallel resistance where the leakage current error due to parasitic parallel resistance may be treated and eliminated as current offset error. Application of M levels of excitation values, where M is greater than or equal to four, eliminates device series parasitic effects, comprised of voltage offset and a series parasitic resistance, and parallel parasitic effects, comprised of current offset error and leakage current error due to parasitic parallel resistance, from temperature measurements.

Abstract: Modulating current of an integrated circuit for signal transmission. The invention may be used in a network device to signal its presence or continued presence to a network router, mid span, hub, or switch, and/or to identify its characteristics or class to control whether and/or what power is applied to the applicable network lines to fully power the network device. Use of the invention in a network environment allows use of certain lines as low voltage signal communication lines for certain network devices, and use of the same lines and/or of different lines for powering other network devices from the same lines at voltages that would damage devices intended for low voltage communication.

Abstract: The present invention provides an improved method and apparatus to measure p-n junction device temperature by testing a device with M-Levels of applied collector current, sensing changes in output characteristics, and calculating the device current offset error and leakage current error due to parasitic parallel resistance where the leakage current error due to parasitic parallel resistance may be treated and eliminated as current offset error. Application of M levels of excitation values, where M is greater than or equal to four, eliminates device series parasitic effects, comprised of voltage offset and a series parasitic resistance, and parallel parasitic effects, comprised of current offset error and leakage current error due to parasitic parallel resistance, from temperature measurements.

Abstract: The present invention offers a low cost, reliable, on chip implementation that takes advantage of the nature of the average current mode topology to detect phase failures within a multi-phase system. The invention further includes sensing average current to the load, generating error voltages and changing duty cycles when the sensed load current is not at the desired level.

Abstract: A circuit utilizable for protecting an integrated circuit feature from electrostatic discharge is disclosed. A first bipolar transistor has its emitter connected to the IC feature and its collector connected to ground. A second bipolar transistor has its emitter connected to the IC feature and its collector connected to its base and to the base of the first bipolar transistor. A field effect transistor has its gate and drain connected to the IC feature and its body connected to its source and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor. A diode has its cathode connected to the body and the source of the field effect transistor and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor.

Abstract: A circuit capable of being integrated into a self-isolated DMOST is driven by a sense resistor that is created from the DMOST drain metallization. The circuit produces an output current that is ratioed with respect to the DMOST current with the ratio being determined by the value of a single resistor. The output current is sourced when the DMOST conducts its source current and the output current is sunk when the DMOST shunt diode conducts. Thus, the circuit not only produces a DMOST current related output it also distinguishes the mode of DMOST conduction.

Abstract: A H-bridge circuit is disclosed using DMOST switches having current sensing parallel connected elements. An op-amp control circuit is coupled to the power and sense sources to force the sense source to the same potential as the power source. The op-amp circuit drives FET output devices which produce an output current proportional to the H-bridge current. A high voltage op-amp configuration is set forth.

Abstract: An integrated circuit is disclosed having a thermal shutdown capability. A single chip bonding pad is coupled to a circuit that will operate the bonding pad at a low potential for normal conditions and will pull it high when a temperature threshold is crossed. Thus, the normally low bonding pad provides a temperature flag. The bonding pad is also coupled to a latch that will hold it high and to a lockout circuit that acts to disable the heat producing chip circuitry. Therefore, when the bonding pad is once driven high the circuits are locked out and will remain out until a start up command is present. This is achieved by either momentarily removing the power supply or by pulling the bonding pad low. Both manual and computer control of the circuit is disclosed.

Abstract: A CMOS relaxation oscillator is disclosed employing a pair of capacitors and individual charging means. A noninverting amplifier comprising two cascaded inverters is provided with a transmission gate input circuit that alternately switches the amplifier input between the two capacitors. A pair of switches coupled respectively across the capacitors alternately discharge them. The resulting oscillator has a frequency determined by the capacitor charging periods. Accordingly, the frequency and duty cycle can be predetermined as desired. The circuit can also be made either power supply tunable or power supply independent.