Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.

Abstract: Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.