Patents by Inventor Manu J. Prakuzhy
Manu J. Prakuzhy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11538742Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: GrantFiled: April 14, 2020Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Publication number: 20200243428Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Inventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Patent number: 10622290Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: GrantFiled: July 11, 2018Date of Patent: April 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Patent number: 10607927Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.Type: GrantFiled: April 13, 2017Date of Patent: March 31, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manu J. Prakuzhy, Siva P. Gurrum, Daryl R. Heussner, Stefan W. Wiktor, Ken Pham
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Publication number: 20200020620Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Siva Prakash Gurrum, Manu J. Prakuzhy, Saumya Gandhi
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Patent number: 10497643Abstract: A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.Type: GrantFiled: May 8, 2018Date of Patent: December 3, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Manu J Prakuzhy
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Publication number: 20190348346Abstract: A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.Type: ApplicationFiled: May 8, 2018Publication date: November 14, 2019Inventors: SIVA PRAKASH GURRUM, MANU J. PRAKUZHY
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Publication number: 20180076116Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.Type: ApplicationFiled: April 13, 2017Publication date: March 15, 2018Inventors: Manu J. Prakuzhy, Siva P. Gurrum, Daryl R. Heussner, Stefan W. Wiktor, Ken Pham
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Patent number: 9373572Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.Type: GrantFiled: October 9, 2015Date of Patent: June 21, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
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Publication number: 20160035655Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.Type: ApplicationFiled: October 9, 2015Publication date: February 4, 2016Inventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
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Patent number: 9165873Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.Type: GrantFiled: September 24, 2014Date of Patent: October 20, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
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Patent number: 9142496Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed.Type: GrantFiled: July 28, 2014Date of Patent: September 22, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott