Abstract: A silicon quantum wire transistor. A silicon substrate is sub-etched leaving a thin ridge (.ltoreq.500 .ANG. tall by .ltoreq.500 .ANG. wide) of silicon a quantum wire, on the substrate surface. An FET may be formed from the quantum wire by depositing or growing gate oxide and depositing gate poly. After defining a gate, the source and drain are defined. Alternatively, an optically activated transistor is formed by defining an emitter and collector and providing a path for illumination to the wire.

Abstract: A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum allow form a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the-germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.

Abstract: A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Abstract: The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.

Abstract: A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.

Abstract: A semiconductor light emitting/detecting device has a first doped silicon layer, an intrinsic silicon epitaxial layer formed on the first doped silicon layer, at least one quantum dot embedded within the intrinsic silicon epitaxial layer, and a second doped silicon layer formed on the second intrinsic silicon epitaxial layer.

Abstract: A method of forming a thin semiconductor layer having ultra-high thickness uniformity and upon which semiconductor structures can subsequently be formed is disclosed. The method comprises providing a primary substrate having a prescribed total thickness variation (TTV). A stack is formed upon the primary substrate for compressing thickness variation to be transferred into the thin semiconductor layer. An epitaxial silicon layer of a desired SOI thickness is formed upon the stack. The epitaxial silicon layer is then bonded to a mechanical substrate to form a bonded substrate pair, the mechanical substrate having a prescribed TTV and the bonded substrate pair having a combined TTV equal to the sum of the TTVs of the primary and mechanical substrates, respectively. The primary substrate is subsequently removed, wherein the combined TTV of the bonded substrate pair is transferred and compressed into the stack by a first compression amount.

Abstract: A semiconductor light emitting/detecting device has a first doped silicon layer, an intrinsic silicon epitaxial layer formed on the first doped silicon layer, at least one quantum dot embedded within the intrinsic silicon epitaxial layer, and a second doped silicon layer formed on the second intrinsic silicon epitaxial layer.

Abstract: A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.

Abstract: A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.

Abstract: A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.