Patents by Inventor Manu Joseph PRAKUZHY

Manu Joseph PRAKUZHY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High current packages with reduced solder layer count
    Patent number: 11901271
    Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: February 13, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yiqi Tang, Liang Wan, William Todd Harrison, Manu Joseph Prakuzhy, Rajen Manicon Murugan
  • HIGH CURRENT PACKAGES WITH REDUCED SOLDER LAYER COUNT
    Publication number: 20230145761
    Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 11, 2023
    Inventors: Yiqi TANG, Liang WAN, William Todd HARRISON, Manu Joseph PRAKUZHY, Rajen Manicon MURUGAN
  • High current packages with reduced solder layer count
    Patent number: 11545420
    Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 3, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Yiqi Tang, Liang Wan, William Todd Harrison, Manu Joseph Prakuzhy, Rajen Manicon Murugan
  • INTEGRATED CIRCUIT HAVING AN ENHANCED THERMAL DISSIPATION PACKAGE
    Publication number: 20220344232
    Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive connector and a die that has an active side and a non-active side. The active side of the die is connected to the electrically conductive connector via interconnects. A molding compound encapsulates the die and portions of the electrically conductive connector. A thermally conductive contact extends from a thermal hotspot on the die to an entry surface of the molding compound.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 27, 2022
    Inventors: MANU JOSEPH PRAKUZHY, SIVA PRAKASH GURRUM, BLAKE BARRETT TRAVIS
  • HIGH CURRENT PACKAGES WITH REDUCED SOLDER LAYER COUNT
    Publication number: 20200258825
    Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 13, 2020
    Inventors: Yiqi TANG, Liang WAN, William Todd HARRISON, Manu Joseph PRAKUZHY, Rajen Manicon MURUGAN