Patents by Inventor Manu Komalan Perumkunnil
Manu Komalan Perumkunnil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11900987Abstract: The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.Type: GrantFiled: November 18, 2020Date of Patent: February 13, 2024Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Mohit Gupta, Manu Komalan Perumkunnil
-
Patent number: 11842758Abstract: According to an aspect there is provided a memory cell. The memory cell comprises: a first and a second electrode; a spin-orbit-torque, SOT, layer comprising a first and a second electrode contact portion arranged in contact with the first and the second electrode, respectively, and an intermediate portion between the first and second electrode contact portions; a first magnetic tunnel junction, MTJ, layer stack arranged in contact with the intermediate portion; and a second MTJ layer stack arranged in contact with the second electrode contact portion and directly above the second electrode. A memory device comprising such a memory cell and a method for writing to such a memory cell are also provided.Type: GrantFiled: December 9, 2021Date of Patent: December 12, 2023Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVENInventors: Mohit Gupta, Kevin Garello, Manu Komalan Perumkunnil
-
Patent number: 11822475Abstract: Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.Type: GrantFiled: December 30, 2021Date of Patent: November 21, 2023Assignee: Imec vzwInventors: Manu Komalan Perumkunnil, Geert Van der Plas
-
Publication number: 20220214972Abstract: Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.Type: ApplicationFiled: December 30, 2021Publication date: July 7, 2022Inventors: Manu Komalan Perumkunnil, Geert Van der Plas
-
Publication number: 20220189523Abstract: According to an aspect there is provided a memory cell. The memory cell comprises: a first and a second electrode; a spin-orbit-torque, SOT, layer comprising a first and a second electrode contact portion arranged in contact with the first and the second electrode, respectively, and an intermediate portion between the first and second electrode contact portions; a first magnetic tunnel junction, MTJ, layer stack arranged in contact with the intermediate portion; and a second MTJ layer stack arranged in contact with the second electrode contact portion and directly above the second electrode. A memory device comprising such a memory cell and a method for writing to such a memory cell are also provided.Type: ApplicationFiled: December 9, 2021Publication date: June 16, 2022Inventors: Mohit GUPTA, Kevin GARELLO, Manu Komalan PERUMKUNNIL
-
Patent number: 11227645Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.Type: GrantFiled: December 6, 2019Date of Patent: January 18, 2022Assignee: IMEC VZWInventors: Sushil Sakhare, Manu Komalan Perumkunnil, Johan Swerts, Gouri Sankar Kar, Trong Huynh Bao
-
Publication number: 20210158859Abstract: The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.Type: ApplicationFiled: November 18, 2020Publication date: May 27, 2021Inventors: Mohit Gupta, Manu Komalan Perumkunnil
-
Patent number: 11004490Abstract: The disclosed technology relates generally to magnetic random access memory, and more particularly to spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM). According to an aspect, a MRAM device comprises a first transistor, a second transistor, and a resistive memory element. The resistive memory element comprises a magnetic tunnel junction (MTJ) pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal. According to another aspect, a method of using the MRAM device is disclosed.Type: GrantFiled: December 16, 2019Date of Patent: May 11, 2021Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Sushil Sakhare, Kevin Garello, Mohit Gupta, Manu Komalan Perumkunnil
-
Publication number: 20200202914Abstract: The disclosed technology relates generally to magnetic random access memory, and more particularly to spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM). According to an aspect, a MRAM device comprises a first transistor, a second transistor, and a resistive memory element. The resistive memory element comprises a magnetic tunnel junction (MTJ) pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal. According to another aspect, a method of using the MRAM device is disclosed.Type: ApplicationFiled: December 16, 2019Publication date: June 25, 2020Inventors: Sushil Sakhare, Kevin Garello, Mohit Gupta, Manu Komalan Perumkunnil
-
Publication number: 20200185016Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.Type: ApplicationFiled: December 6, 2019Publication date: June 11, 2020Inventors: Sushil Sakhare, Manu Komalan Perumkunnil, Johan Swerts, Gouri Sankar Kar, Trong Huynh Bao
-
Patent number: 10325647Abstract: A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.Type: GrantFiled: December 6, 2017Date of Patent: June 18, 2019Assignees: IMEC VZW, VRIJE UNIVERSITEIT BRUSSEL, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Sushil Sakhare, Trong Huynh Bao, Manu Komalan Perumkunnil
-
Publication number: 20180174644Abstract: A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.Type: ApplicationFiled: December 6, 2017Publication date: June 21, 2018Inventors: Sushil Sakhare, Trong Huynh Bao, Manu Komalan Perumkunnil