Abstract: Circuits for generating random weights, such as for neuromorphic processors, include a first voltage node (VDD) for providing a supply voltage for the circuit and a second voltage node (VG) at a given electric potential. A first circuit element (Ma1) has a first electric current carrier concentration for outputting a first circuit element output signal. A second circuit element (Mb1) has a second electric current carrier concentration for outputting a second circuit element output signal. The first and second circuit elements are located between the first and second voltage nodes, which have a given voltage difference therebetween. The first and second circuit element output signals are different due to the first and second electric carrier concentrations being mismatched. The circuit further includes a subtraction unit configured to generate a respective random weight, which is represented by a difference between the first and second circuit element output signals.

Abstract: A differential memristive circuit includes a normaliser; a first memristor connected between first top and bottom nodes, the first memristive element having a first adjustable resistance value; a first switch connected between the first bottom node and the normaliser; a second memristor connected between a second top node and a second bottom node the second memristor having a second adjustable resistance value; a second switch connected between the second bottom node and the normaliser; and a set of voltage sources that generate voltages greater than 0V. The set of voltage sources generate a first voltage value across the first memristor and a second voltage value across the second memristor. A first output signal depends on the first adjustable resistance value, while a second output signal depends on the second adjustable resistance value. A memristive circuit net output signal is obtained as the difference between the first and second output signals.

Abstract: A differential memristive circuit includes a normaliser; a first memristor connected between first top and bottom nodes, the first memristive element having a first adjustable resistance value; a first switch connected between the first bottom node and the normaliser; a second memristor connected between a second top node and a second bottom node the second memristor having a second adjustable resistance value; a second switch connected between the second bottom node and the normaliser; and a set of voltage sources that generate voltages greater than 0V. The set of voltage sources generate a first voltage value across the first memristor and a second voltage value across the second memristor. A first output signal depends on the first adjustable resistance value, while a second output signal depends on the second adjustable resistance value. A memristive circuit net output signal is obtained as the difference between the first and second output signals.