Patents by Inventor Manuel ALDEGUNDE RODRIGUEZ

Manuel ALDEGUNDE RODRIGUEZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic random-access memory pass transistors with statistical variations in leakage currents
    Patent number: 11494539
    Abstract: The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 8, 2022
    Assignee: Synopsys, Inc.
    Inventors: Salvatore Maria Amoroso, Plamen A. Asenov, Jaehyun Lee, Andrew R. Brown, Manuel Aldegunde Rodriguez, Binjie Cheng, Andrew John Pender, David T. Reid
  • DYMANIC RANDOM-ACCESS MEMORY PASS TRANSISTORS WITH STATISTICAL VARIATIONS IN LEAKAGE CURRENTS
    Publication number: 20210248296
    Abstract: The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.
    Type: Application
    Filed: February 10, 2021
    Publication date: August 12, 2021
    Inventors: Salvatore Maria AMOROSO, Plamen A. ASENOV, Jaehyun LEE, Andrew R. BROWN, Manuel ALDEGUNDE RODRIGUEZ, Binjie CHENG, Andrew John PENDER, David T. REID