Patents by Inventor Manuel Aldrete
Manuel Aldrete has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369230Abstract: A package comprising a first metallization portion, a first integrated device, an interconnection die, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The interconnection die is coupled to the first metallization portion. The second metallization portion coupled to the first metallization portion through the interconnection die such that the first integrated device and the interconnection die are located between the first metallization portion and the second metallization portion. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Yangyang SUN, Manuel ALDRETE, Lily ZHAO
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Patent number: 11804428Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.Type: GrantFiled: November 13, 2020Date of Patent: October 31, 2023Assignee: QUALCOMM INCORPORATEDInventors: Wen Yin, Yonghao An, Manuel Aldrete
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Publication number: 20220157705Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Wen YIN, Yonghao AN, Manuel ALDRETE
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Publication number: 20210280507Abstract: A package comprising a substrate comprising a first surface and a second surface, a passive device coupled to the first surface of the substrate, a first encapsulation layer located over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device, an integrated device coupled to the second surface of the substrate, a second encapsulation layer located over the second surface of the substrate, wherein the second encapsulation layer encapsulates the integrated device, a plurality of through encapsulation layer interconnects coupled to the substrate, a plurality of encapsulation layer interconnects coupled to the plurality of through encapsulation layer interconnects, and at least one dummy interconnect located in the second encapsulation layer, wherein the at least one dummy interconnect is located vertically over a back side of the integrated device.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Manuel ALDRETE, Milind SHAH, Srikanth KULKARNI
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Patent number: 10879191Abstract: An RF/EMI shield has a substrate, a plurality of solder balls on a first side of the substrate, and a plurality of wire-bonds on a periphery of the first side of the substrate to form a shield which can be soldered in a surface mount process directly around components needing shielding. Each of the plurality of wire-bonds has a width selected as a fraction of the wavelength of interest.Type: GrantFiled: January 7, 2019Date of Patent: December 29, 2020Assignee: QUALCOMM IncorporatedInventors: Daniel Daeik Kim, Manuel Aldrete, Babak Nejati
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Publication number: 20200219822Abstract: An RF/EMI shield has a substrate, a plurality of solder balls on a first side of the substrate, and a plurality of wire-bonds on a periphery of the first side of the substrate to form a shield which can be soldered in a surface mount process directly around components needing shielding. Each of the plurality of wire-bonds has a width selected as a fraction of the wavelength of interest.Type: ApplicationFiled: January 7, 2019Publication date: July 9, 2020Inventors: Daniel Daeik KIM, Manuel ALDRETE, Babak NEJATI
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Patent number: 10511268Abstract: An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.Type: GrantFiled: June 28, 2017Date of Patent: December 17, 2019Assignee: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, Manuel Aldrete, Bonhoon Koo
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Patent number: 10490472Abstract: Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.Type: GrantFiled: August 30, 2017Date of Patent: November 26, 2019Assignee: QUALCOMM IncorporatedInventors: Jie Fu, Hong Bok We, Manuel Aldrete
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Publication number: 20190341352Abstract: A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.Type: ApplicationFiled: May 2, 2018Publication date: November 7, 2019Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Manuel ALDRETE, David Fraser RAE
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Patent number: 10431511Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.Type: GrantFiled: May 1, 2017Date of Patent: October 1, 2019Assignee: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, Shu Zhang, Bonhoon Koo, Manuel Aldrete, Jie Fu, Chin-Kwan Kim, Babak Nejati, Husnu Ahmet Masaracioglu
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Patent number: 10418333Abstract: Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes an IC and a shielding sidewall disposed adjacent to the IC. In certain aspects, the IC comprises a first layer coupled to the shielding sidewall, a second layer comprising a first signal path, and a third layer disposed below the first layer and coupled to the shielding sidewall, wherein the second layer is disposed between the first layer and the third layer. In some cases, the IC also includes a plurality of vias configured to couple the first layer to the third layer, wherein at least a portion of the first signal path is disposed in an inner shielding region that spans from the first layer to the third layer and spans from the shielding sidewall to the plurality of vias.Type: GrantFiled: May 22, 2018Date of Patent: September 17, 2019Assignee: QUALCOMM IncorporatedInventors: Daeik Kim, Jie Fu, Manuel Aldrete
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Patent number: 10325855Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.Type: GrantFiled: March 18, 2016Date of Patent: June 18, 2019Assignee: QUALCOMM IncorporatedInventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim
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Patent number: 10325859Abstract: Some features pertain to a stacked package apparatus that includes a shield at least partially surrounding the apparatus, a first substrate including a plurality of first pads, the plurality of first pads coupled to the shield, and a second substrate, the second substrate over the first substrate and coupled to the first substrate, the second substrate including a plurality of second pads, the plurality of second pads coupled to the shield.Type: GrantFiled: April 3, 2018Date of Patent: June 18, 2019Assignee: QUALCOMM IncorporatedInventors: Daeik Kim, Jie Fu, Manuel Aldrete
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Patent number: 10319694Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.Type: GrantFiled: August 10, 2016Date of Patent: June 11, 2019Assignee: QUALCOMM IncorporatedInventors: Daniel Daeik Kim, Jie Fu, Manuel Aldrete, Jonghae Kim, Changhan Hobie Yun, David Francis Berdy, Chengjie Zuo, Mario Francisco Velez
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Publication number: 20190067141Abstract: Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Jie FU, Hong Bok WE, Manuel ALDRETE
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Publication number: 20190006999Abstract: An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Daeik Daniel KIM, Manuel ALDRETE, Bonhoon KOO
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Publication number: 20180316319Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.Type: ApplicationFiled: May 1, 2017Publication date: November 1, 2018Inventors: Daeik Daniel KIM, Shu ZHANG, Bonhoon KOO, Manuel ALDRETE, Jie FU, Chin-Kwan KIM, Babak NEJATI, Husnu Ahmet MASARACIOGLU
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Publication number: 20180228016Abstract: In a package such as a radio frequency (RF) module, an external shield may be provided to shield the package from external influences as well as to shield the devices within the package from undesirable affecting devices outside of the package. The package may also include an internal shield to suppress adverse effects of the signal generated by an aggressor device within the external shield to other devices within the external shield.Type: ApplicationFiled: February 9, 2017Publication date: August 9, 2018Inventors: Daeik Daniel KIM, Jie FU, Manuel ALDRETE, Babak NEJATI, Husnu Ahmet MASARACIOGLU
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Publication number: 20180047687Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.Type: ApplicationFiled: August 10, 2016Publication date: February 15, 2018Inventors: Daeik Daniel KIM, Jie FU, Manuel ALDRETE, Jonghae KIM, Changhan Hobie YUN, David Francis BERDY, Chengjie ZUO, Mario Francisco VELEZ
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Publication number: 20170271266Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.Type: ApplicationFiled: March 18, 2016Publication date: September 21, 2017Inventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim