Abstract: The present invention relates to a computer-implemented method capable of automatically classifying and differentiating biliary lesions in images obtained from a digital cholangioscopy system, characterizing them according to their malignant potential, through the classification of pixels as a malignant lesion, or benign lesion, followed by a characterization stage and indexing of such lesions according to a set of morphologic characteristics with clinical relevance, namely the presence/absence of tumor vessels, the presence/absence of papillary projections, the presence/absence of intraductal nodules and the presence/absence of tumor masses.

Abstract: The present invention relates to a bicycle crank axle torque modulation device (1), comprising a bracket (3) including a spring-bearing assembly (4), wherein each end of the spring (7) thereof is connected to each of the bearings (6) by a connection member (8); an eccentric surface (5) for driving said spring-bearing assembly (4), which is in permanent contact with the bearings (6) of said spring-bearing assembly (4), wherein one of the bracket (3) and the eccentric surface (5) is arranged to be attached to a bicycle frame and the other to be attached to said bicycle crank axle. The invention further relates to a torque tuning process, a kit comprising a crank axle and the modulation device, and to a bike including the same.

Abstract: Disclosed embodiments include a recommendation system and apparatus comprising a tendencies based collaborative filtering method. In a particular embodiment, the Tendencies Based Collaborative Filtering Method (TBCFM) is based on the user mean, the item mean, the user tendency calculated using a User Tendency Calculation Method (UTCM); and the item tendency calculated using a Item Tendency Calculation Method (ITCM).

Abstract: An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The ESD protection structure also includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. The ESD protection structure also includes first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively.

Abstract: A MOSFET structure for use in an ESD protection device that includes a semiconductor substrate (e.g., a silicon substrate) of a first conductivity type with a gate insulation layer (e.g., a gate silicon dioxide layer) thereon. A patterned gate layer overlies the gate insulation layer, source and drain regions of a second conductivity type are disposed in the semiconductor substrate, and an LDD source extension region of the second conductivity type is located adjacent to the source region. Furthermore, a channel region of the first conductivity type is disposed underneath the gate insulation layer and extends from the LDD source extension region to the drain region. The absence of an LDD drain extension region, combined with the presence of an LDD source extension region, provides for superior snap-back performance (i.e., a relatively low first breakdown voltage and a relatively low holding voltage).

Abstract: An ESD protection structure for use with ICs that can protect from ESD events of both positive and negative polarities, has a low snapback holding voltage and a high maximum snapback current, and is relatively immune to thermal overheating. The structure includes a semiconductor substrate of a first conductivity type (typically P-type), as well as first and second well regions of a second conductivity type (typically N-type) that are separated a gap region of the first conductivity type and disposed in the substrate. A gate silicon dioxide layer overlies the gap region and a gate electrode overlies the gate silicon dioxide layer. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively.