Patents by Inventor Manuel Collados Asensio

Manuel Collados Asensio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8198949
    Abstract: The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 12, 2012
    Assignee: ST-Ericsson SA
    Inventors: Xin He, Jan Van Sinderen, Manuel Collados Asensio, Nenad Pavlovic
  • Publication number: 20110261914
    Abstract: The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal.
    Type: Application
    Filed: July 1, 2009
    Publication date: October 27, 2011
    Inventors: Xin He, Jan Van Sinderen, Manuel Collados Asensio, Nenad Pavlovic
  • Publication number: 20100052806
    Abstract: Modulators for amplitude-modulating signals defined by phase information and envelope codes are provided with first transistors for receiving the phase information and second transistors for receiving the envelope codes. The first main electrode of one transistor is coupled to the second main electrode of the other transistor and the other second main electrode constitutes an output of the modulator. This modulator can be used in any kind of transistor environment and is simple and low cost. The doped areas of the coupled first and second main electrodes comprise an overlap to reduce cross-talk and to reduce silicon area. Polar transmitters are provided with this modulator and with a circuit for generating a phase/frequency code and the envelope code and with an oscillator for receiving the phase/frequency code and for generating the phase information. A phase shift between the phase information and the envelope code reduce aliases.
    Type: Application
    Filed: April 19, 2007
    Publication date: March 4, 2010
    Inventors: Paulus T.M. Van Zeijl, Manuel Collados Asensio