Abstract: A Radio Frequency Identification (RFID) reader is provided that receives a digital input signal, converts the digital input signal to an analog input signal, and determines whether the digital input signal is an unmodulated signal or is modulated with information. When the digital input signal is modulated with information, the RFID reader filters the analog input signal to produce a filtered analog input signal and transmits the filtered signal. When the digital input signal is an unmodulated signal, the RFID reader bypasses the filtering of the analog input signal to produce an unfiltered analog input signal and transmits the unfiltered analog input signal.

Abstract: A Radio Frequency Identification (RFID) reader is provided that receives a digital input signal, converts the digital input signal to an analog input signal, and determines whether the digital input signal is an unmodulated signal or is modulated with information. When the digital input signal is modulated with information, the RFID reader filters the analog input signal to produce a filtered analog input signal and transmits the filtered signal. When the digital input signal is an unmodulated signal, the RFID reader bypasses the filtering of the analog input signal to produce an unfiltered analog input signal and transmits the unfiltered analog input signal.

Abstract: A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.