Patents by Inventor Manuel L. Torreno, Jr.
Manuel L. Torreno, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5917222Abstract: A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices.Type: GrantFiled: February 20, 1998Date of Patent: June 29, 1999Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Ronald N. Parker, Manuel L. Torreno, Jr., deceased
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Patent number: 5911104Abstract: A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices.Type: GrantFiled: February 20, 1998Date of Patent: June 8, 1999Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Ronald N. Parker, Manuel L. Torreno, Jr., deceased
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Patent number: 5811850Abstract: A process for the fabrication of an improved LDMOS transistor, and such an improved LDMOS transistor are provided. The improved LDMOS transistor is in a semiconductor layer of a first conductivity type. The transistor has a source and drain of a second conductivity type (opposite the first conductivity type) and a channel of the first conductivity type with a conductive gate insulatively disposed over the channel. A low-voltage tank of the second conductivity type is used to contain the drain drift region and because of its lower sheet resistance provides a lower R.sub.DS (on). This tank of the second conductivity type extends from the field oxide at the exterior perimeter of the drain region, joins with the channel region and extends below the gate oxide and field oxide associated therewith.Type: GrantFiled: March 13, 1996Date of Patent: September 22, 1998Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Manuel L. Torreno, Jr., deceased
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Patent number: 5767551Abstract: A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices.Type: GrantFiled: March 4, 1997Date of Patent: June 16, 1998Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Ronald N. Parker, Manuel L. Torreno, Jr., deceased
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Patent number: 5585294Abstract: A process for the fabrication of an improved LDMOS transistor, and such an improved LDMOS transistor are provided. The improved LDMOS transistor is in a semiconductor layer of a first conductivity type. The transistor has a source and drain of a second conductivity type (opposite the first conductivity type) and a channel of the first conductivity type with a conductive gate insulatively disposed over the channel. A low-voltage tank of the second conductivity type is used to contain the drain drift region and because of its lower sheet resistance provides a lower R.sub.DS (on). This tank of the second conductivity type extends from the field oxide at the exterior perimeter of the drain region, joins with the channel region and extends below the gate oxide and field oxide associated therewith.Type: GrantFiled: October 14, 1994Date of Patent: December 17, 1996Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Manuel L. Torreno, Jr., deceased
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Patent number: 5491105Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions (103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).Type: GrantFiled: September 9, 1994Date of Patent: February 13, 1996Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Manuel L. Torreno, Jr., deceased, Georges Falessi
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Patent number: 5242841Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions (103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).Type: GrantFiled: March 25, 1992Date of Patent: September 7, 1993Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Manuel L. Torreno, Jr. deceased, George Falessi
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Polysilicon self-aligned bipolar device including trench isolation and process of manufacturing same
Patent number: 5104816Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer. The method includes forming an isolation trench, viewed in plan, having corners that are angled at about 45 degrees.Type: GrantFiled: March 5, 1990Date of Patent: April 14, 1992Assignee: Texas Instruments IncorporatedInventors: Douglas P. Verret, Jeffrey E. Brighton, Deems R. Hollingsworth, Manuel L. Torreno, Jr. -
Patent number: 5017510Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).Type: GrantFiled: May 25, 1989Date of Patent: May 21, 1991Assignee: Texas Instruments IncorporatedInventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr.
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Patent number: 4966865Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.Type: GrantFiled: September 16, 1988Date of Patent: October 30, 1990Assignee: Texas Instruments IncorporatedInventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton
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Patent number: 4958210Abstract: Premature avalanche breakdown resulting from high electric fields produced by metal interconnections crossing underlying high conductivity regions of an integrated circuit is eliminated by selectively providing discontinuities in the high conductivity regions underlying the metal interconnection paths.Type: GrantFiled: November 20, 1989Date of Patent: September 18, 1990Assignee: General Electric CompanyInventors: Surinder Krishna, Manuel L. Torreno, Jr., Michael S. Adler
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Patent number: 4862243Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).Type: GrantFiled: June 1, 1987Date of Patent: August 29, 1989Assignee: Texas Instruments IncorporatedInventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr.
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Patent number: 4799099Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer.Type: GrantFiled: November 19, 1986Date of Patent: January 17, 1989Assignee: Texas Instruments IncorporatedInventors: Douglas P. Verret, Jeffrey E. Brighton, Deems R. Hollingsworth, Manuel L. Torreno, Jr.
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Patent number: 4795722Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.Type: GrantFiled: February 5, 1987Date of Patent: January 3, 1989Assignee: Texas Instruments IncorporatedInventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton
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Patent number: 4789885Abstract: A method of forming double polysilicon contacts to underlying diffused regions of a semiconductor body which includes forming first and second level electrically conductive silicon layers over the body which contact respective first and second diffused regions of the body. The diffused regions are formed such that said first diffused region is ringed by said second diffused region. The second silicon layer thus overlaps the first silicon layer. The top surfaces of the first and second silicon layers are silicided such that the silicide formed over the first silicon layer is aligned with the edge of the second silicon layer.Type: GrantFiled: February 10, 1987Date of Patent: December 6, 1988Assignee: Texas Instruments IncorporatedInventors: Jeffrey E. Brighton, Deems R. Hollingsworth, Michael Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Charles W. Sullivan
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Patent number: 4753709Abstract: A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.Type: GrantFiled: February 5, 1987Date of Patent: June 28, 1988Assignee: Texas Instuments IncorporatedInventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton
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Patent number: 4260908Abstract: A high power microelectronic switching circuit is interfaced with a fiberoptic data link, whereby inductive or resistive loads up to 20 amperes are switched, with a forward voltage drop of less than one volt. An input signal of one-half milliwatt is passed to the gate of a V-MOS FET power device, which drives a PNP output transistor to switch a power supply to a circuit load.Type: GrantFiled: August 30, 1978Date of Patent: April 7, 1981Assignee: Texas Instruments IncorporatedInventors: Joe D. Mings, Manuel L. Torreno, Jr.
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Patent number: 3995309Abstract: Isolation junctions in semiconductor devices are formed by selected regions of specified conductivity wherein each region has a substantially uniform thickness and resistivity throughout the region. The material of the selected regions is recrystallized semiconductor material with solid solubility of the dopant impurity.Type: GrantFiled: November 1, 1974Date of Patent: November 30, 1976Assignee: General Electric CompanyInventor: Manuel L. Torreno, Jr.
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Patent number: 3988763Abstract: Isolation junctions in semiconductor devices are formed by selected regions of specified conductivity wherein each region has a substantially uniform thickness and resistivity throughout the region. The material of the selected regions is recrystallized semiconductor material with solid solubility of the dopant impurity.Type: GrantFiled: March 10, 1975Date of Patent: October 26, 1976Assignee: General Electric CompanyInventor: Manuel L. Torreno, Jr.
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Patent number: 3982269Abstract: A homogeneous integrated power structure embodies solid state control or signal devices and power devices integrated monolithically to achieve optimum physical characteristics of each device embodied therein at economical cost of manufacturing the same. The devices are electrically isolated from each other by a P-N junction isolation grid produced by the thermomigration of metal-rich wires through a semiconductor substrate by thermal gradient zone melting processing techniques.Type: GrantFiled: November 22, 1974Date of Patent: September 21, 1976Assignee: General Electric CompanyInventors: Manuel L. Torreno, Jr., Bruno F. Kurz, deceased, Surinder Krishna