Patents by Inventor Manuel Le Gallo-Bourdeau
Manuel Le Gallo-Bourdeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127009Abstract: A probability distribution corresponding to the kernel function is determined and weights are sampled from the determined probability distribution corresponding to the given kernel function. Memristive devices of an analog crossbar are programmed based on the sampled weights, where each memristive device of the analog crossbar is configured to represent a corresponding weight. Two matrix-vector multiplication operations are performed on an analog input x and an analog input y using the programmed crossbar and a dot product is computed on results of the matrix-vector multiplication operations.Type: ApplicationFiled: September 30, 2022Publication date: April 18, 2024Inventors: Julian Röttger Büchel, Abbas Rahimi, Manuel Le Gallo-Bourdeau, Irem Boybat Kara, Abu Sebastian
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Patent number: 11935590Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.Type: GrantFiled: March 29, 2022Date of Patent: March 19, 2024Assignee: International Business Machines CorporationInventors: Ghazi Sarwat Syed, Manuel Le Gallo-Bourdeau, Abu Sebastian
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Publication number: 20240086682Abstract: A 3D compute-in-memory accelerator system and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores, each in-memory core including multiple tiers of in-memory compute cells. One or more tiers of in-memory compute cells correspond to an expert sub-model of the MoE model. One or more expert sub-models are selected for activation propagation based on a function-based routing, the tiers of the corresponding experts being activated based on this function. In one embodiment, this function is a hash-based tier selection function used for dynamic routing of inputs and output activations. In embodiments, the function is applied to select a single expert or multiple experts with input data-based or with layer-activation-based MoEs for single tier activation. Further, the system is configured as a multi-model system with single expert model selection or with a multi-model system with multi-expert selection.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Inventors: Julian Roettger Buechel, Manuel Le Gallo-Bourdeau, Irem Boybat Kara, Abbas Rahimi, Abu Sebastian
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Publication number: 20230317153Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Ghazi Sarwat Syed, Manuel Le Gallo-Bourdeau, Abu Sebastian
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Publication number: 20230305893Abstract: Provided is a method, device, and computer program product for programming a set of first elements onto a computational memory. The computational memory allows for performing a computation task from a set of second elements that encode the set of first elements in the computational memory, respectively. The method includes performing the computation task by the computational memory using the set of second elements and adapting at least part of the set of second elements in the computational memory based on a measured result of the computation task, until the measured result of the computation task fulfils an accuracy condition.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Inventors: Manuel Le Gallo-Bourdeau, Abu Sebastian, Frédéric Elias Odermatt, Julian Buechel
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Patent number: 11665984Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.Type: GrantFiled: December 7, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Ghazi Sarwat Syed, Vara Sudananda Prasad Jonnalagadda, Benedikt Kersting, Manuel Le Gallo-Bourdeau, Abu Sebastian
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Patent number: 11665985Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.Type: GrantFiled: November 23, 2020Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Benedikt Kersting, Ghazi Sarwat Syed, Vara Sudananda Prasad Jonnalagadda, Manuel Le Gallo-Bourdeau, Abu Sebastian, Timothy Mathew Philip
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Patent number: 11663458Abstract: A method of operating a neuromorphic system is provided. The method includes applying voltage signals across input lines of a crossbar array structure, the crossbar array structure including rows and columns interconnected at junctions via programmable electronic devices, the rows including the input lines for applying voltage signals across the electronic devices and the columns including output lines for outputting currents. The method also includes correcting, via a correction unit connected to the output lines, each of the output currents obtained at the output lines according to an affine transformation to compensate for temporal conductance variations in the electronic devices.Type: GrantFiled: April 8, 2020Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Vinay Manikrao Joshi, Simon Haefeli, Manuel Le Gallo-Bourdeau, Irem Boybat Kara, Abu Sebastian
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Publication number: 20230097217Abstract: Techniques are provided for learning static bound management parameters for an analog resistive processing unit system which is configured for neuromorphic computing. For example, a system comprises one or more processors which are configured to: perform a first training process to train a first artificial neural network model; perform a second training process to retrain the first artificial neural network model using matrix-vector compute operations which are a function of bound management parameters of an analog resistive processing unit system, to thereby generate a second artificial neural network model with learned static bound management parameters; and configure the resistive processing unit system to implement the second artificial neural network model and the learned static bound management parameters.Type: ApplicationFiled: September 25, 2021Publication date: March 30, 2023Inventors: Malte Johannes Rasch, Manuel Le Gallo-Bourdeau, HsinYu Tsai, Charles Mackin, Nandakumar Sasidharan Rajalekshmi, An Chen
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Patent number: 11574209Abstract: A system for hyper-dimensional computing for inference tasks may be provided. The device comprises an item memory for storing hyper-dimensional item vectors, a query transformation unit connected to the item memory, the query transformation unit being adapted for forming a hyper-dimensional query vector from a query input and hyper-dimensional base vectors stored in the item memory, and an associative memory adapted for storing a plurality of hyper-dimensional profile vectors and for determining a distance between the hyper-dimensional query vector and the plurality of hyper-dimensional profile vectors, wherein the item memory and the associative memory are adapted for in-memory computing using memristive devices.Type: GrantFiled: May 30, 2019Date of Patent: February 7, 2023Assignees: International Business Machines Corporation, ETH ZURICH (EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZURICH)Inventors: Kumudu Geethan Karunaratne, Manuel Le Gallo-Bourdeau, Giovanni Cherubini, Abu Sebastian, Abbas Rahimi, Luca Benini
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Patent number: 11556312Abstract: A co-processor for performing a matrix multiplication of an input matrix with a data matrix in one step may be provided. The co-processor receives input signals for the input matrix as optical signals. A plurality of photonic memory elements is arranged at crossing points of an optical waveguide crossbar array. The plurality of memory elements is configured to store values of the data matrix. Input signals are connected to input lines of the optical waveguide crossbar array. Output lines of the optical waveguide crossbar array represent a dot-product between a respective column of the optical waveguide crossbar array and the received input signals, and values of elements of the input matrix to be multiplied with the data matrix correspond to light intensities received at input lines of the respective photonic memory elements. Additionally, different wavelengths are used for each column of the input matrix optical signals.Type: GrantFiled: July 10, 2020Date of Patent: January 17, 2023Assignees: International Business Machines Corporation, Oxford University Innovation Limited, University of Exeter, University of MuensterInventors: Abu Sebastian, Manuel Le Gallo-Bourdeau, Christopher David Wright, Nathan Youngblood, Harish Bhaskaran, Xuan Li, Wolfram Pernice, Johannes Feldmann
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Patent number: 11531898Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n?1 and (p+n+m)=N where m?0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.Type: GrantFiled: May 16, 2019Date of Patent: December 20, 2022Assignee: International Business Machines CorporationInventors: Manuel Le Gallo-Bourdeau, Riduan Khaddam-Aljameh, Lukas Kull, Pier Andrea Francese, Thomas H. Toifl, Abu Sebastian, Evangelos Stavros Eleftheriou
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Publication number: 20220383063Abstract: The present disclosure relates to a method for representing an ordered group of symbols with a hypervector. The method comprises sequentially applying on at least part of the input hypervector associated with a current symbol a predefined number of circular shift operations associated with the current symbol, resulting in a shifted hypervector. A rotate operation may be applied on the shifted hypervector, resulting in an output hypervector. If the current symbol is not the last symbol of the ordered group of symbols the output hypervector may be provided as the input hypervector associated with a subsequent symbol of the current symbol; otherwise, the output hypervector of the last symbol of the ordered group of symbols may be provided as a hypervector that represents the ordered group of symbols.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Kumudu Geethan Karunaratne, Abbas Rahimi, Manuel Le Gallo-Bourdeau, Giovanni Cherubini, Abu Sebastian
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Publication number: 20220293174Abstract: A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines.Type: ApplicationFiled: March 9, 2021Publication date: September 15, 2022Inventors: Riduan Khaddam-Aljameh, Manuel Le Gallo-Bourdeau, Abu Sebastian
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Patent number: 11436302Abstract: The present disclosure relates to an electronic system for computing items of an outer product matrix, for each item of at least part of the items of the matrix. The system is configured to receive a pair of real numbers of two vectors, the pair corresponding to the item. The system is further configured to compute a stochastic representation of the real numbers resulting in two sets of bits, the set of bits comprising a subset of bits representing the real number and a sign bit indicative of the sign of the real number. The system is further configured to perform a sequence of digital operations using the two sets of bits to provide a representation of the item.Type: GrantFiled: June 7, 2019Date of Patent: September 6, 2022Assignee: International Business Machines CorporationInventors: Vinay Manikrao Joshi, Abu Sebastian, Manuel Le Gallo-Bourdeau, Irem Boybat Kara, Christophe Piveteau
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Patent number: 11386319Abstract: Methods and apparatus are provided for training an artificial neural network, having a succession of neuron layers with interposed synaptic layers each storing a respective set of weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for at least one of the synaptic layers, providing a plurality Pl of arrays of memristive devices, each array storing the set of weights of that synaptic layer Sl in respective memristive devices, and, in a signal propagation operation, supplying respective subsets of the signals to be weighted by the synaptic layer Sl in parallel to the Pl arrays. The method also includes, in a weight-update calculation operation, calculating updates to respective weights stored in each of the Pl arrays in dependence on signals propagated by the neuron layers.Type: GrantFiled: March 14, 2019Date of Patent: July 12, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manuel Le Gallo-Bourdeau, Nandakumar Sasidharan Rajalekshmi, Christophe Piveteau, Irem Boybat Kara, Abu Sebastian, Evangelos Stavros Eleftheriou
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Patent number: 11373092Abstract: Methods are provided for training weights of an artificial neural network to be implemented by inference computing apparatus in which the trained weights are stored as programmed conductance states of respective predetermined memristive devices. Such a method includes deriving for the memristive devices a probability distribution indicating distribution of conductance errors for the devices in the programmed conductance states. The method further comprises, in a digital computing apparatus: training the weights via an iterative training process in which the weights are repeatedly updated in response to processing by the network of training data which is propagated over the network via the weights; and applying noise dependent on said probability distribution to weights used in the iterative training process.Type: GrantFiled: April 10, 2019Date of Patent: June 28, 2022Assignee: International Business Machines CorporationInventors: Christophe Piveteau, Abu Sebastian, Manuel Le Gallo-Bourdeau, Vinay Manikrao Joshi
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Publication number: 20220180167Abstract: The present disclosure relates to a method for classifying a query information element using the similarity between the query information element and a set of support information elements. A resulting set of similarity scores is transformed using a sharpening function such that the transformed scores are decreasing as negative similarity scores increase and the transformed scores are increasing as positive similarity scores increase. A class of the query information element is determined based on the transformed similarity scores.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Inventors: Kumudu Geethan Karunaratne, Manuel Le Gallo-Bourdeau, Giovanni Cherubini, Abu Sebastian, Abbas Rahimi
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Patent number: 11348002Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of layers of neurons interposed with layers of synapses. A set of crossbar arrays of memristive devices, connected between row and column lines, implements the layers of synapses. Each memristive device stores a weight for a synapse interconnecting a respective pair of neurons in successive neuron layers. The training method includes performing forward propagation, backpropagation and weight-update operations of an iterative training scheme by applying input signals, associated with respective neurons, to row or column lines of the set of arrays to obtain output signals on the other of the row or column lines, and storing digital signal values corresponding to the input and output signals. The weight-update operation is performed by calculating digital weight-correction values for respective memristive devices, and applying programming signals to those devices to update the stored weights.Type: GrantFiled: June 29, 2018Date of Patent: May 31, 2022Assignee: International Business Machines CorporationInventors: Irem Boybat Kara, Evangelos Stavros Eleftheriou, Manuel Le Gallo-Bourdeau, Nandakumar Sasidharan Rajalekshmi, Abu Sebastian
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Publication number: 20220165948Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.Type: ApplicationFiled: November 23, 2020Publication date: May 26, 2022Inventors: Benedikt Kersting, Ghazi Sarwat Syed, Vara Sudananda Prasad Jonnalagadda, Manuel Le Gallo-Bourdeau, Abu Sebastian, Timothy Mathew Philip