Patents by Inventor Manuel Le Gallo-Bourdeau

Manuel Le Gallo-Bourdeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250005431
    Abstract: Systems and methods for optimizing conductance ranges of a plurality of unit cells are described. A processor can define a plurality of initial conductance ranges for a plurality of unit cells arranged in a crossbar arrangement. The plurality of unit cells can include non-volatile memory (NVM) devices. An initial conductance range is defined per column of unit cells in the crossbar arrangement. The processor can use the plurality of initial conductance ranges to encode parameter values in a circuit model of the analog memory device. The processor can input a plurality of sample inputs into the circuit model to determine an output current distribution correlated to a plurality of products between the plurality of sample inputs and the parameter values. The processor can determine, based on at least one property of the output current distribution, an optimal conductance range for the plurality of unit cells.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Corey Liam Lammie, Manuel Le Gallo-Bourdeau, Benedikt Kersting, Abu Sebastian, Julian Röttger Büchel
  • Publication number: 20240419971
    Abstract: Precision of a neural processing apparatus comprising two in-memory compute (IMC) units is controlled, wherein the IMC units include a first IMC unit and a second IMC unit, each designed to perform vector-matrix multiplication (VMM) to produce analog output signals. An artificial neural network (ANN) model is trained to learn its parameters (including synaptic weight values) in accordance with a dual objective. The ANN model comprises two neural layers, these including a first neural layer and a second neural layer. The method further comprises storing the synaptic weight values of the parameters learned in the two IMC units to respectively map the first neural layer and the second neural layer onto the first IMC unit and the second IMC unit. The second IMC unit is designed to perform VMM operations based on analog input signals generated from activation values produced by the first neural layer.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 19, 2024
    Inventors: Julian Röttger Büchel, Manuel Le Gallo-Bourdeau, Abu Sebastian
  • Publication number: 20240420762
    Abstract: The present disclosure relates to a method for compensating non-ideality of a neuromorphic memory device. The neuromorphic memory device comprising a crossbar array of wordlines and bitlines. The crossbar array comprises a block of wordline and bitline segments, wherein memory elements of the block are programmed to represent array values. The device is configured for applying a set of inputs to the initial wordlines for performing dot products. The method comprises: performing at least one of: wordline expansion or bitline expansion of the block. The set of inputs may be applied to the initial wordlines of the expanded block and in case the bitline expansion is performed an additional input may be applied to the additional wordlines of the expanded block. The currents flowing in the bitlines of the expanded block may be measured. The dot products may be determined using the measured currents.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 19, 2024
    Inventors: Benedikt Kersting, Athanasios Vasilopoulos, Manuel Le Gallo-Bourdeau, Julian Röttger Büchel, Abu Sebastian
  • Patent number: 12141692
    Abstract: The present disclosure relates to a method for classifying a query information element using the similarity between the query information element and a set of support information elements. A resulting set of similarity scores is transformed using a sharpening function such that the transformed scores are decreasing as negative similarity scores increase and the transformed scores are increasing as positive similarity scores increase. A class of the query information element is determined based on the transformed similarity scores.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kumudu Geethan Karunaratne, Manuel Le Gallo-Bourdeau, Giovanni Cherubini, Abu Sebastian, Abbas Rahimi
  • Patent number: 12125531
    Abstract: A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: October 22, 2024
    Assignee: International Business Machines Corporation
    Inventors: Riduan Khaddam-Aljameh, Manuel Le Gallo-Bourdeau, Abu Sebastian
  • Patent number: 12093802
    Abstract: The exemplary embodiments disclose a method, a computer program product, and a computer system for a gated recurrent neural network (RNN). The exemplary embodiments may include providing an element processor, providing a distinct memory array for a respective set of one or more elements of a hidden state vector, storing in the memory array a group of columns of weight matrices that enable a computation of the set of one or more elements, computing one or more elements of each of multiple activation vectors using a set of one or more columns of the group of columns associated with each of the multiple activation vectors, and performing by the element processor an elementwise gating operation on computed elements, resulting in the set of one or more elements.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 17, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manuel Le Gallo-Bourdeau, Vinay Manikrao Joshi, Abu Sebastian, Milos Stanisavljevic
  • Publication number: 20240289607
    Abstract: A method, computer program product, and system to generate a processor design via a deep neural network is provided. A processor selects an architecture search space and a hardware components space. A processor selects an initial deep neural network from the architecture search space. A processor determines an initial current chip design for executing the current deep neural network, wherein the initial chip design has a hardware performance metric for implementing the current deep neural network. A processor repeatedly executes an optimization method, the optimization method comprising modifying the chip design one or more times using components from the hardware components space and optimizing the current deep neural network by selecting a deep neural network from the architecture search space. A processor provides the optimized chip design and the specific deep neural network for performing the machine learning task.
    Type: Application
    Filed: February 27, 2023
    Publication date: August 29, 2024
    Inventors: Irem Boybat Kara, Hadjer Benmeziane, Manuel Le Gallo-Bourdeau, Kaoutar El Maghraoui, Malte Johannes Rasch, HsinYu Tsai
  • Patent number: 12050977
    Abstract: The present disclosure relates to a method for representing an ordered group of symbols with a hypervector. The method comprises sequentially applying on at least part of the input hypervector associated with a current symbol a predefined number of circular shift operations associated with the current symbol, resulting in a shifted hypervector. A rotate operation may be applied on the shifted hypervector, resulting in an output hypervector. If the current symbol is not the last symbol of the ordered group of symbols the output hypervector may be provided as the input hypervector associated with a subsequent symbol of the current symbol; otherwise, the output hypervector of the last symbol of the ordered group of symbols may be provided as a hypervector that represents the ordered group of symbols.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: July 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kumudu Geethan Karunaratne, Abbas Rahimi, Manuel Le Gallo-Bourdeau, Giovanni Cherubini, Abu Sebastian
  • Publication number: 20240160348
    Abstract: The invention is notably directed to a method of programming memory elements of an in-memory computing (IMC) device. The IMC applies a SET signal to the K memory elements of said each cell to set each of the K memory elements to a SET state and reading K conductance values of the K memory elements in the SET state. The IMC adjusts, based on the K conductance values read and the target conductance value, a conductance value of at least one of the K memory elements to match a summed conductance of the K memory elements of said each cell with the target conductance value. The IMC maximizes a number of the K memory elements that are either in their SET state or in a RESET state of zero conductance nominal value, such that at most one of the K memory elements is neither in a SET state nor in a RESET state.
    Type: Application
    Filed: April 24, 2023
    Publication date: May 16, 2024
    Inventors: Manuel Le Gallo-Bourdeau, Athanasios Vasilopoulos, Benedikt Kersting, Julian Röttger Büchel, Abu Sebastian
  • Publication number: 20240127009
    Abstract: A probability distribution corresponding to the kernel function is determined and weights are sampled from the determined probability distribution corresponding to the given kernel function. Memristive devices of an analog crossbar are programmed based on the sampled weights, where each memristive device of the analog crossbar is configured to represent a corresponding weight. Two matrix-vector multiplication operations are performed on an analog input x and an analog input y using the programmed crossbar and a dot product is computed on results of the matrix-vector multiplication operations.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 18, 2024
    Inventors: Julian Röttger Büchel, Abbas Rahimi, Manuel Le Gallo-Bourdeau, Irem Boybat Kara, Abu Sebastian
  • Patent number: 11935590
    Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: March 19, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ghazi Sarwat Syed, Manuel Le Gallo-Bourdeau, Abu Sebastian
  • Publication number: 20240086682
    Abstract: A 3D compute-in-memory accelerator system and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores, each in-memory core including multiple tiers of in-memory compute cells. One or more tiers of in-memory compute cells correspond to an expert sub-model of the MoE model. One or more expert sub-models are selected for activation propagation based on a function-based routing, the tiers of the corresponding experts being activated based on this function. In one embodiment, this function is a hash-based tier selection function used for dynamic routing of inputs and output activations. In embodiments, the function is applied to select a single expert or multiple experts with input data-based or with layer-activation-based MoEs for single tier activation. Further, the system is configured as a multi-model system with single expert model selection or with a multi-model system with multi-expert selection.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Julian Roettger Buechel, Manuel Le Gallo-Bourdeau, Irem Boybat Kara, Abbas Rahimi, Abu Sebastian
  • Publication number: 20230317153
    Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Ghazi Sarwat Syed, Manuel Le Gallo-Bourdeau, Abu Sebastian
  • Publication number: 20230305893
    Abstract: Provided is a method, device, and computer program product for programming a set of first elements onto a computational memory. The computational memory allows for performing a computation task from a set of second elements that encode the set of first elements in the computational memory, respectively. The method includes performing the computation task by the computational memory using the set of second elements and adapting at least part of the set of second elements in the computational memory based on a measured result of the computation task, until the measured result of the computation task fulfils an accuracy condition.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: Manuel Le Gallo-Bourdeau, Abu Sebastian, Frédéric Elias Odermatt, Julian Buechel
  • Patent number: 11665984
    Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ghazi Sarwat Syed, Vara Sudananda Prasad Jonnalagadda, Benedikt Kersting, Manuel Le Gallo-Bourdeau, Abu Sebastian
  • Patent number: 11663458
    Abstract: A method of operating a neuromorphic system is provided. The method includes applying voltage signals across input lines of a crossbar array structure, the crossbar array structure including rows and columns interconnected at junctions via programmable electronic devices, the rows including the input lines for applying voltage signals across the electronic devices and the columns including output lines for outputting currents. The method also includes correcting, via a correction unit connected to the output lines, each of the output currents obtained at the output lines according to an affine transformation to compensate for temporal conductance variations in the electronic devices.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Vinay Manikrao Joshi, Simon Haefeli, Manuel Le Gallo-Bourdeau, Irem Boybat Kara, Abu Sebastian
  • Patent number: 11665985
    Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Benedikt Kersting, Ghazi Sarwat Syed, Vara Sudananda Prasad Jonnalagadda, Manuel Le Gallo-Bourdeau, Abu Sebastian, Timothy Mathew Philip
  • Publication number: 20230097217
    Abstract: Techniques are provided for learning static bound management parameters for an analog resistive processing unit system which is configured for neuromorphic computing. For example, a system comprises one or more processors which are configured to: perform a first training process to train a first artificial neural network model; perform a second training process to retrain the first artificial neural network model using matrix-vector compute operations which are a function of bound management parameters of an analog resistive processing unit system, to thereby generate a second artificial neural network model with learned static bound management parameters; and configure the resistive processing unit system to implement the second artificial neural network model and the learned static bound management parameters.
    Type: Application
    Filed: September 25, 2021
    Publication date: March 30, 2023
    Inventors: Malte Johannes Rasch, Manuel Le Gallo-Bourdeau, HsinYu Tsai, Charles Mackin, Nandakumar Sasidharan Rajalekshmi, An Chen
  • Patent number: 11574209
    Abstract: A system for hyper-dimensional computing for inference tasks may be provided. The device comprises an item memory for storing hyper-dimensional item vectors, a query transformation unit connected to the item memory, the query transformation unit being adapted for forming a hyper-dimensional query vector from a query input and hyper-dimensional base vectors stored in the item memory, and an associative memory adapted for storing a plurality of hyper-dimensional profile vectors and for determining a distance between the hyper-dimensional query vector and the plurality of hyper-dimensional profile vectors, wherein the item memory and the associative memory are adapted for in-memory computing using memristive devices.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 7, 2023
    Assignees: International Business Machines Corporation, ETH ZURICH (EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZURICH)
    Inventors: Kumudu Geethan Karunaratne, Manuel Le Gallo-Bourdeau, Giovanni Cherubini, Abu Sebastian, Abbas Rahimi, Luca Benini
  • Patent number: 11556312
    Abstract: A co-processor for performing a matrix multiplication of an input matrix with a data matrix in one step may be provided. The co-processor receives input signals for the input matrix as optical signals. A plurality of photonic memory elements is arranged at crossing points of an optical waveguide crossbar array. The plurality of memory elements is configured to store values of the data matrix. Input signals are connected to input lines of the optical waveguide crossbar array. Output lines of the optical waveguide crossbar array represent a dot-product between a respective column of the optical waveguide crossbar array and the received input signals, and values of elements of the input matrix to be multiplied with the data matrix correspond to light intensities received at input lines of the respective photonic memory elements. Additionally, different wavelengths are used for each column of the input matrix optical signals.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: January 17, 2023
    Assignees: International Business Machines Corporation, Oxford University Innovation Limited, University of Exeter, University of Muenster
    Inventors: Abu Sebastian, Manuel Le Gallo-Bourdeau, Christopher David Wright, Nathan Youngblood, Harish Bhaskaran, Xuan Li, Wolfram Pernice, Johannes Feldmann