Abstract: A projector panel includes pixel display, a display controller, and a pattern generator. The pattern generator is operative to output pixel data indicative of at least one application specific predetermined pattern. In a particular embodiment, the projector panel is a liquid-crystal-on-silicon panel. In another particular embodiment, the projector panel is adapted for selective use in either structured light projection systems or conventional video projection systems.

Abstract: Techniques and mechanisms for exchanging sets of video data each via multiple channels. In an embodiment, a first data set is distributed across the multiple channels according to a first mapping of the multiple channels each to a different respective one of multiple data types, where each of the multiple data types corresponds to a different respective dimension of a color space. In another embodiment, a second data set is distributed across the multiple channels according to a second mapping of the multiple channels each to a different respective one of the multiple data types, where the second mapping is different from the first mapping.

Abstract: Techniques and mechanisms for circuitry to provide video data for loading to a buffer. In an embodiment, a loader circuit receives video data and determines MX data for a video frame and NZ data for the video frame, wherein M and N are different respective dimensions of a color space, and wherein X is a first encoding type and Z is a second encoding type. The first MX data includes data representing a first portion of a color component value, and the first NZ data includes data representing a second portion of that color component value. In another embodiment, the loader circuit sends the MX data via a first channel while sending the NZ data via a second channel to a random access buffer.

Abstract: A projector panel includes pixel display, a display controller, and a pattern generator. The pattern generator is operative to output pixel data indicative of at least one application specific predetermined pattern. In a particular embodiment, the projector panel is a liquid-crystal-on-silicon panel. In another particular embodiment, the projector panel is adapted for selective use in either structured light projection systems or conventional video projection systems.

Abstract: Techniques and mechanisms for circuitry to provide video data for loading to a buffer. In an embodiment, a loader circuit receives video data and determines MX data for a video frame and NZ data for the video frame, wherein M and N are different respective dimensions of a color space, and wherein X is a first encoding type and Z is a second encoding type. The first MX data includes data representing a first portion of a color component value, and the first NZ data includes data representing a second portion of that color component value. In another embodiment, the loader circuit sends the MX data via a first channel while sending the NZ data via a second channel to a random access buffer.

Abstract: Techniques and mechanisms for exchanging sets of video data each via multiple channels. In an embodiment, a first data set is distributed across the multiple channels according to a first mapping of the multiple channels each to a different respective one of multiple data types, where each of the multiple data types corresponds to a different respective dimension of a color space. In another embodiment, a second data set is distributed across the multiple channels according to a second mapping of the multiple channels each to a different respective one of the multiple data types, where the second mapping is different from the first mapping.

Abstract: An electronic system is described herein, the apparatus including at least two devices requiring access to memory, a memory controller, and a memory, the memory being coupled to an output of the memory controller. The memory controller includes at least one input and at least one output; one memory controller input being operatively coupled to at least one of the devices through a shared bus, and one memory controller output being operatively coupled to at least one device through a shared bus. The shared bus includes a plurality of device select lines, a plurality of address lines, a plurality of write data lines, a plurality of read data lines, a plurality of read select lines, and at least two device_request lines.

Abstract: A novel apparatus and method is disclosed to assure validity of data accessed from synchronous memory during a "read" operation, wherein the synchronous memory is operating synchronously at a high frequency system clock. The invention comprises a programmable delay module which generates a skewed clock signal which is used to clock in data read from the synchronous memory. The programmable delay module generates the skewed clock signal by adding programmable time delays to the system clock signal. The inserted delay increases the data valid window time available for the "read" operation and allows sufficient setup and hold time for valid data to be read by a memory controller.

Abstract: A novel apparatus and method is disclosed to assure validity of data accessed from synchronous memory during a "read" operation, wherein the synchronous memory is operating synchronously at a high frequency system clock. The invention comprises a programmable delay module which generates a skewed clock signal which is used to clock in data read from the synchronous memory. The programmable delay module generates the skewed clock signal by adding programmable time delays to the system clock signal. The inserted delay increases the data valid window time available for the "read" operation and allows sufficient setup and hold time for valid data to be read by a memory controller.