Patents by Inventor Manuel M. Mejia
Manuel M. Mejia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6798242Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.Type: GrantFiled: April 29, 2003Date of Patent: September 28, 2004Assignee: Altera CorporationInventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Publication number: 20030201794Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of sub-regions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.Type: ApplicationFiled: April 29, 2003Publication date: October 30, 2003Applicant: Altera CorporationInventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Patent number: 6577160Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors).Type: GrantFiled: June 10, 2002Date of Patent: June 10, 2003Assignee: Altera CorporationInventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Publication number: 20030076130Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.Type: ApplicationFiled: June 10, 2002Publication date: April 24, 2003Inventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Patent number: 6417694Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.Type: GrantFiled: September 19, 2001Date of Patent: July 9, 2002Assignee: Altera CorporationInventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Publication number: 20020041191Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.Type: ApplicationFiled: September 19, 2001Publication date: April 11, 2002Applicant: Altera CorporationInventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Patent number: 6300794Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.Type: GrantFiled: January 20, 2000Date of Patent: October 9, 2001Assignee: Altera CorporationInventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Patent number: 5977793Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.Type: GrantFiled: May 13, 1997Date of Patent: November 2, 1999Assignee: Altera CorporationInventors: Srinivas T. Reddy, Richard G. Cliff, Christopher F. Lane, Ketan H. Zaveri, Manuel M. Mejia, David Jefferson, Bruce B. Pedersen, Andy L. Lee
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Patent number: 5872529Abstract: A dynamic run-length encoding scheme compresses data streams more effectively than conventional run-length encoding, which uses a fixed group length for encoding. With dynamic compression according to the invention, the group length is dynamically modified by the bitstream itself. This allows for greater efficiency in compression. As with run-length encoding, the actual compression ratio is a function of the particular bitstream. However, for identical bitstreams, the invention achieves greater compression than run-length encoding. The invention has applications in compressing data that is used to program a programmable logic device, thereby effectively increasing the capacity of storage, such as Serial EPROM's, used for PLD programming files.Type: GrantFiled: July 16, 1997Date of Patent: February 16, 1999Assignee: Altera CorporationInventor: Manuel M. Mejia