Patents by Inventor Manuel Olivier Gautho

Manuel Olivier Gautho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10255228
    Abstract: One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 9, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Xiaogang Qiu, Jack Hilaire Choquette, Manuel Olivier Gautho, Ming Y. (Michael) Siu
  • Patent number: 8639882
    Abstract: Methods and apparatus for source operand collector caching. In one embodiment, a processor includes a register file that may be coupled to storage elements (i.e., an operand collector) that provide inputs to the datapath of the processor core for executing an instruction. In order to reduce bandwidth between the register file and the operand collector, operands may be cached and reused in subsequent instructions. A scheduling unit maintains a cache table for monitoring which register values are currently stored in the operand collector. The scheduling unit may also configure the operand collector to select the particular storage elements that are coupled to the inputs to the datapath for a given instruction.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: January 28, 2014
    Assignee: Nvidia Corporation
    Inventors: Jack Hilaire Choquette, Manuel Olivier Gautho, John Erik Lindholm
  • Publication number: 20130159628
    Abstract: Methods and apparatus for source operand collector caching. In one embodiment, a processor includes a register file that may be coupled to storage elements (i.e., an operand collector) that provide inputs to the datapath of the processor core for executing an instruction. In order to reduce bandwidth between the register file and the operand collector, operands may be cached and reused in subsequent instructions. A scheduling unit maintains a cache table for monitoring which register values are currently stored in the operand collector. The scheduling unit may also configure the operand collector to select the particular storage elements that are coupled to the inputs to the datapath for a given instruction.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Jack Hilaire CHOQUETTE, Manuel Olivier Gautho, John Erik Lindholm
  • Publication number: 20130145124
    Abstract: One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Inventors: Xiaogang Qiu, Jack Hilaire Choquette, Manuel Olivier Gautho, Ming Y. (Michael) Siu