Abstract: An autonomous mobile device has a tower extending from a main body. The tower pans from left to right. An extensible mast may extend through, and pan with, the tower. An upper section is attached to the tower by a hinge and may tilt with respect to the tower. The upper section may include a touchscreen or other devices. An assembly with separate pan and tilt motors allows for the tower and attached upper section to pan while also allowing the upper section to tilt independently of the panning motion. The tilt motor is within the portion of the assembly rotated by the pan motor. The tilt motor drives a worm gear in the tower to rotate a tilt axle. An asymmetric friction hinge connects to the upper section to the tilt axle. Rotating the tilt motor rotates the worm gear, rotating the tilt axle and the attached upper section.

Abstract: A circuit for a multistage sequential data process includes a plurality of memory units. Each memory unit is associated with a stage of the sequential data process which, for each data set inputted to the stage, the stage provides an intermediate data set for storage in the associated memory unit for use in at least one subsequent stage of the sequential data process, where each of the plurality of memory units is sized based on relative locations of the stage providing the intermediate data set and the at least one subsequent stage in the sequential data process.

Abstract: A memory control unit for handling data stored in a memory device includes a first interface to an interconnection with at least one memory bank; a second interface for communicating with a data requesting unit; and a memory quantization unit. The memory quantization unit is configured to: obtain, via the first interface, a first weight value from the at least one memory bank; quantize the first weight value to generate at least one quantized weight value having a shorter bit length than a bit length of the first weight value; and communicate the at least one quantized weight value to the data requesting unit via the second interface.

Abstract: The present disclosure is drawn to the reduction of parameters in fully connected layers of neural networks. For a layer whose output is defined by y=Wx, where y is the output vector, x is the input vector, and W is a matrix of connection parameters, vectors uij and vij are defined and submatrices Wi,j are computed as the outer product of uij and vij, so that Wi,j=vij?uij, and W is obtained by appending submatrices Wi,j.

Abstract: A system for training a neural network includes a first set of neural network units and a second set of neural networking units. Each neural network unit in the first set is configured to compute parameter update data for one of a plurality of instances of a first portion of the neural network. Each neural network unit in the first set includes a communication interface for communicating its parameter update data for combination with parameter update data from another neural network unit in the first set. Each neural network unit in the second set is configured to compute parameter update data for one of a plurality of instances of a second portion of the neural network. Each neural network unit in the second set includes a communication interface for communicating its parameter update data for combination with parameter update data from another neural network unit in the second set.

Abstract: A memory control unit for handling data stored in a memory device includes a first interface to an interconnection with at least one memory bank; a second interface for communicating with a data requesting unit; and a memory quantization unit. The memory quantization unit is configured to: obtain, via the first interface, a first weight value from the at least one memory bank; quantize the first weight value to generate at least one quantized weight value having a shorter bit length than a bit length of the first weight value; and communicate the at least one quantized weight value to the data requesting unit via the second interface.

Abstract: The present disclosure is drawn to the reduction of parameters in fully connected layers of neural networks. For a layer whose output is defined by y=Wx, where y is the output vector, x is the input vector, and W is a matrix of connection parameters, vectors uij and ij are defined and submatrices Wi,j are computed as the outer product of uij and ij, so that Wi,j=ijuij, and W is obtained by appending submatrices Wi,j.

Abstract: A circuit for a multistage sequential data process includes a plurality of memory units. Each memory unit is associated with a stage of the sequential data process which, for each data set inputted to the stage, the stage provides an intermediate data set for storage in the associated memory unit for use in at least one subsequent stage of the sequential data process, where each of the plurality of memory units is sized based on relative locations of the stage providing the intermediate data set and the at least one subsequent stage in the sequential data process.

Abstract: Systems, devices and methods for data compression using history search for dictionary based compression. Systems, devices and methods may use parallel processing techniques for data compression and encoding. Systems, devices and methods may provide memory search techniques for hardware.

Abstract: Systems, devices and methods for data compression using history search for dictionary based compression. Systems, devices and methods may use parallel processing techniques for data compression and encoding. Systems, devices and methods may provide memory search techniques for hardware.

Abstract: Systems, devices and methods for data compression using history search for dictionary based compression. Systems, devices and methods may use parallel processing techniques for data compression and encoding. Systems, devices and methods may provide memory search techniques for hardware.

Abstract: Systems, devices and methods for data compression using history search for dictionary based compression. Systems, devices and methods may use parallel processing techniques for data compression and encoding. Systems, devices and methods may provide memory search techniques for hardware.

Abstract: Systems, devices and methods for data compression using history search for dictionary based compression. Systems, devices and methods may use parallel processing techniques for data compression and encoding. Systems, devices and methods may provide memory search techniques for hardware.

Abstract: Systems, devices and methods for data compression using history search for dictionary based compression. Systems, devices and methods may use parallel processing techniques for data compression and encoding. Systems, devices and methods may provide memory search techniques for hardware.

Abstract: A lighting system and method are provided for controlling a PWM duty cycle. The lighting system is provided with at least one device that is configured to emit light in response to receiving electrical power. The lighting system includes a power circuit and a feedback circuit. The power circuit is configured to selectively supply power to the device at a duty cycle corresponding to a first mode and a second mode, wherein the duty cycle of the first mode is less than 10% of the duty cycle of the second mode. The feedback circuit is configured to provide a feedback signal that is indicative of the energy provided to the device. The power circuit is further configured to disable power to the device during the first mode in response to the energy being greater than a threshold energy value, thereby adjusting the duty cycle.

Abstract: A lighting system and method are provided for controlling a PWM duty cycle. The lighting system is provided with at least one device that is configured to emit light in response to receiving electrical power. The lighting system includes a power circuit and a feedback circuit. The power circuit is configured to selectively supply power to the device at a duty cycle corresponding to a first mode and a second mode, wherein the duty cycle of the first mode is less than 10% of the duty cycle of the second mode. The feedback circuit is configured to provide a feedback signal that is indicative of the energy provided to the device. The power circuit is further configured to disable power to the device during the first mode in response to the energy being greater than a threshold energy value, thereby adjusting the duty cycle.

Abstract: An architecture for a scalable computing machine built using configurable processing elements, such as FPGAs, is provided. The machine can enable implementation of large scale computing applications using a heterogeneous combination of hardware accelerators and embedded microprocessors spread across many FPGAs, all interconnected by a flexible communication network structure.