Patents by Inventor Manuel Suárez Cambre

Manuel Suárez Cambre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three dimensional CMOS image processor for feature detection
    Patent number: 8942481
    Abstract: Disclose embodiments include an image processor for feature detection comprising a single non-planar chip containing a plurality of integrated sensing and processing resources across two or more layers adapted to capture image frames and extract image features. In a particular embodiment, the non-planar chip is a three dimensional CMOS integrated circuit (3D CMOS IC) with vertical distribution of sensing and processing resources across two or more vertical integrated circuit layers. The 3D CMOS IC implements two or more feature detectors in a single chip by reusing a plurality of circuits employed for gradient and keypoint detection. Feature detectors include a scale invariant feature transform detector (SIFT), a Harris-based feature detector, and a Hessian-based feature detector.
    Type: Grant
    Filed: March 11, 2012
    Date of Patent: January 27, 2015
    Assignees: Universidad de Santiago de Compostela, Consejo Superior de Investigaciones Cientificas, Universidad de Sevilla
    Inventors: Manuel Suárez Cambre, Víctor Manuel Brea Sánchez, Fernando Rafael Pardo Seco, Ángel Rodríguez Vázquez, Ricardo Carmona Galán
  • IMAGE PROCESSOR FOR FEATURE DETECTION
    Publication number: 20130236048
    Abstract: Disclose embodiments include an image processor for feature detection comprising a single non-planar chip containing a plurality of integrated sensing and processing resources across two or more layers adapted to capture image frames and extract image features. In a particular embodiment, the non-planar chip is a three dimensional CMOS integrated circuit (3D CMOS IC) with vertical distribution of sensing and processing resources across two or more vertical integrated circuit layers. The 3D CMOS IC implements two or more feature detectors in a single chip by reusing a plurality of circuits employed for gradient and keypoint detection. Feature detectors include a scale invariant feature transform detector (SIFT), a Harris-based feature detector, and a Hessian-based feature detector.
    Type: Application
    Filed: March 11, 2012
    Publication date: September 12, 2013
    Applicants: CONSEJO SUPERIOR DE INVESTIGACIONES CIENTIFICAS, UNIVERSIDAD DE SEVILLA
    Inventors: Angel Rodriguez Vazquez, Fernando Rafael Pardo Seco, Manuel Suarez Cambre, Ricardo Carmona Galan, Victor Manuel Brea Sanchez