Patents by Inventor Manuel Torreno

Manuel Torreno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods
    Patent number: 5296393
    Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (139/140); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (141, 142) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (143); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (144, 145); vertical and lateral annular DMOS transistors (146, 147); a Schottky diode (148); and a FAMOS EPROM cell (149). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.
    Type: Grant
    Filed: August 3, 1992
    Date of Patent: March 22, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Michael C. Smayling, Louis Hutter, Georges Falessi, James R. Todd, Manuel Torreno