Patents by Inventor Manuj Ayodhyawasi
Manuj Ayodhyawasi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112748Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.Type: ApplicationFiled: July 31, 2023Publication date: April 4, 2024Applicant: STMicroelectronics International N.V.Inventors: Tanuj KUMAR, Hitesh CHAWLA, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240112728Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.Type: ApplicationFiled: September 11, 2023Publication date: April 4, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Dipti ARYA, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20240071429Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Nitin CHAWLA, Promod KUMAR, Kedar Janardan DHORI, Manuj AYODHYAWASI
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Publication number: 20240071439Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Nitin CHAWLA, Promod KUMAR, Kedar Janardan DHORI, Manuj AYODHYAWASI
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Publication number: 20240071546Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Hitesh CHAWLA, Tanuj KUMAR, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240069096Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.Type: ApplicationFiled: July 31, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Patent number: 11900240Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.Type: GrantFiled: September 16, 2020Date of Patent: February 13, 2024Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Giuseppe Desoli, Manuj Ayodhyawasi, Thomas Boesch, Surinder Pal Singh
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Publication number: 20240045589Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Giuseppe DESOLI, Anuj GROVER, Thomas BOESCH, Surinder Pal SINGH, Manuj AYODHYAWASI
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Publication number: 20230410862Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.Type: ApplicationFiled: April 19, 2023Publication date: December 21, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230410892Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.Type: ApplicationFiled: April 20, 2023Publication date: December 21, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Harsh RAWAT, Manuj AYODHYAWASI
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Patent number: 11836346Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: GrantFiled: May 12, 2022Date of Patent: December 5, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Pal Singh, Manuj Ayodhyawasi
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Publication number: 20230386564Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.Type: ApplicationFiled: April 20, 2023Publication date: November 30, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Nitin CHAWLA, Promod KUMAR, Harsh RAWAT, Manuj AYODHYAWASI
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Publication number: 20230386565Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.Type: ApplicationFiled: April 19, 2023Publication date: November 30, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Harsh RAWAT, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230386566Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.Type: ApplicationFiled: April 20, 2023Publication date: November 30, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Harsh RAWAT, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230102492Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.Type: ApplicationFiled: September 27, 2022Publication date: March 30, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230012567Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.Type: ApplicationFiled: June 21, 2022Publication date: January 19, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230012303Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.Type: ApplicationFiled: June 29, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Harsh RAWAT, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230008275Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.Type: ApplicationFiled: June 20, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Nitin CHAWLA, Promod KUMAR, Manuj AYODHYAWASI, Harsh RAWAT
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Publication number: 20230009329Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.Type: ApplicationFiled: June 27, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230008833Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.Type: ApplicationFiled: June 27, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI