Patents by Inventor Manuj Nahar

Manuj Nahar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10650978
    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Beth R. Cook, Manuj Nahar, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20200075732
    Abstract: A method of forming a semiconductor structure includes forming a first material over a base material by vapor phase epitaxy. The first material has a crystalline portion and an amorphous portion. The amorphous portion of the first material is removed by abrasive planarization. At least a second material is formed by vapor phase epitaxy over the crystalline portion of first material. The second material has a crystalline portion and an amorphous portion. The amorphous portion of the second material is removed by abrasive planarization. A semiconductor structure formed by such a method includes the substrate, the first material, the second material, and optionally, an oxide material between the first material and the second material. The substrate, the first material, and the second material define a continuous crystalline structure. Semiconductor structures, memory devices, and systems are also disclosed.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Michael Mutch, Manuj Nahar
  • Publication number: 20200075713
    Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Michael Mutch, Manuj Nahar, Wayne I. Kinney
  • Publication number: 20200066513
    Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Manuj Nahar, Darwin Franseda Fan, Junting Liu-Norrod, Michael Mutch
  • Publication number: 20200066516
    Abstract: Some embodiments include a semiconductor structure having a laminate which has first regions alternating with second regions. The first regions include silicon, and the second regions include germanium. Some embodiments include a method of forming a semiconductor structure. The semiconductor structure may correspond to at least a portion of an active region of a transistor. A first semiconductor material is deposited with a first deposition process. The first semiconductor material includes silicon. The first deposition process is intermittently interrupted to etch a surface of the deposited first semiconductor material and to deposit a second semiconductor material with a second deposition process. The second semiconductor material includes germanium. The semiconductor structure is at least partially crystalline.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Manuj Nahar, Darwin Franseda Fan
  • Patent number: 10553673
    Abstract: A method used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between comprises forming an insulative first material comprising an amorphous insulative metal oxide. The amorphous insulative metal oxide is reduced in a reducing-ambient to form a conductive second material from the insulative first material. Such reducing in the reducing-ambient both (a) removes oxygen from and changes the stoichiometry of the metal oxide, and (b) crystallizes the metal oxide into a crystalline state that is conductive.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Vassil N. Antonov
  • Publication number: 20190198606
    Abstract: A method used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between comprises forming an insulative first material comprising an amorphous insulative metal oxide. The amorphous insulative metal oxide is reduced in a reducing-ambient to form a conductive second material from the insulative first material. Such reducing in the reducing-ambient both (a) removes oxygen from and changes the stoichiometry of the metal oxide, and (b) crystallizes the metal oxide into a crystalline state that is conductive.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Inventors: Manuj Nahar, Vassil N. Antonov
  • Publication number: 20190189357
    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: Ashonita A. Chavan, Beth R. Cook, Manuj Nahar, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20190066917
    Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventors: Manuj Nahar, Ashonita A. Chavan
  • Publication number: 20180102374
    Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy, Manuj Nahar
  • Patent number: 9876018
    Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: January 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy, Manuj Nahar
  • Publication number: 20170162587
    Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy, Manuj Nahar