Abstract: The present invention discloses a debugging unit and a processor. The debugging unit includes; a register, adapted to sample input data under control of a clock signal; and a dock control unit, adapted to generate a control signal based on a clock enable signal to control the clock signal, so that the register is controlled to sample the input data in a validity period of the clock signal when the control signal is valid. The present invention also discloses a corresponding system-on-chip and an intelligent device including the system-on-chip.

Abstract: A processor achieving a zero-overhead loop, includes instruction stream control circuitry and loop control circuitry. The loop control circuitry includes loop address detecting circuitry and loop end determining circuitry. By combining instructions and hardware, the loop control circuitry eliminates additional control instructions required b each loop iteration and can achieve loop acceleration with zero overhead, thereby improving the loop execution efficiency.

Abstract: The present disclosure provides a processor achieving a zero-overhead loop, the processor comprising an instruction stream control circuitry and a loop control circuitry, wherein the loop control circuitry comprises a loop address detecting circuitry and a loop end determining circuitry. The present disclosure eliminates, by means of combining instructions and hardware, additional control instructions required by each loop iteration and can achieve loop acceleration with zero overhead, thereby improving the loop execution efficiency.

Abstract: The present invention discloses a debugging unit and a processor. The debugging unit includes; a register, adapted to sample input data under control of a clock signal; and a dock control unit, adapted to generate a control signal based on a clock enable signal to control the clock signal, so that the register is controlled to sample the input data in a validity period of the clock signal when the control signal is valid.

Abstract: The present invention discloses an instruction processing device, including a first register adapted to store a source data address, a second register adapted to store a source data length, a third vector register adapted to store target data, a decoder and an execution unit. The decoder is adapted to receive and decode a data loading instruction. The data loading instruction instructs that the first register serves as a first operand, the second register serves as a second operand, and the third vector register serves as a third operand.