Abstract: A method and program product comprises displaying a graphic area in a page of an e-book comprising a first three dimensional object being operative for animating and interacting. A first control object is displayed on the page. The first control object comprises a second three dimensional object being operative for animating and interacting for navigation to a next page in the e-book. A second control object on the page. The second control object comprises a third three dimensional object being operative for animating and interacting for navigation to a previous page in the e-book. A text area is displayed in the page.

Abstract: A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block.

Abstract: A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block.