Abstract: A heart valve prosthesis device includes a stent and leaflets. The stent includes an annular part and guide parts. A first end of the annular part includes cell sections arranged in sequence in a circumferential direction of the annular part. The guide parts are arranged at intervals in the circumferential direction of the annular part, one side of each guide part is connected to a corresponding cell section, and the other side gradually tapers to an end where a retrieval cell is provided for a pulling wire to pass through. Each guide part includes a first region being the retrieval cell, a second region aligned with the first region and configured as a central region, and a third region and a fourth region distributed on two sides of the central region in the circumferential direction of the annular part.

Abstract: A bendable sheath and a delivery system using the bendable sheath. The bendable sheath comprises a tube body (3). The tube body (3) comprises a distal end and a proximal end. A tube wall of the tube body (3) is connected to a pull wire (8). One end of the pull wire (8) extends towards the proximal end of the tube body (3), and the other end is connected to the tube body (3) near the distal end of the tube body (3). The pull wire (8) comprises at least a section thereof disposed freely outside the tube body (3) and near the distal end of the tube body (3). The pull wire (8) in the bendable sheath comprises the section disposed freely outside the sheath tube body (3) and, when pulled, the section is disposed so as to facilitate the application of force. The section moves relative to the tube body (3), such that a force application point is adaptively changed.

Abstract: The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.

Abstract: Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and a plurality of shielding columns. The core layer has an accommodating space, in which the accommodating space has an inner sidewall. The electronic component is disposed in the accommodating space. The first shielding ring wall is disposed in the accommodating space and covers the inner sidewall, in which the first shielding ring wall surrounds the electronic component and is not in contact with the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The shielding columns are disposed in the first insulating layer.

Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and a plurality of shielding columns. The core layer has an accommodating space, in which the accommodating space has an inner sidewall. The electronic component is disposed in the accommodating space. The first shielding ring wall is disposed in the accommodating space and covers the inner sidewall, in which the first shielding ring wall surrounds the electronic component and is not in contact with the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The shielding columns are disposed in the first insulating layer.

Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and first shielding columns. The core layer includes an accommodating space, and the accommodating space has an inner side wall. The first shielding ring wall is disposed in the accommodating space and covers the inner side wall, in which the first shielding ring wall surrounds the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding columns are disposed in the first insulating layer.

Abstract: A method of removing a hard mask layer includes providing a gate. A hard mask layer covers and contacts a top surface of the gate. Two spacer structures respectively contacts two sides of the gate. Two first spacers are respectively disposed on the two spacer structures. Later, a wet etching process is performed to remove the hard mask layer and the first spacers and keep the spacer structures. An etchant is utilized in the wet etching process. A selective etching ratio of the silicon nitride to silicon oxide of the etchant is more than 90. The etchant includes Si(OH)4. A concentration of Si(OH)4.is greater than or equal to 3.95 ppm and smaller than or equal to 10 ppm.

Abstract: A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 ?m. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.

Abstract: A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 ?m. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.

Abstract: Match-paired monoclonal antibodies against major royal jelly protein 4 (MRJP4) are secreted by hybridoma cell lines having microbial deposit numbers of CGMCC No. 17294 and CGMCC No. 17295, which are used in an ELISA kit and a colloidal gold immunoassay strip for detecting the MRJP4. The positive and MRJP4-specific cell lines are obtained by cell fusion using an antigen of MRJP4 recombinant protein and a cross-reaction with other major royal jelly proteins. The MRJP4 recombinant protein is used as an antigen to obtain several positive cell lines by cell fusion and two MRJP4-specific fusion cell lines are obtained by a cross-reaction with other major royal jelly proteins. Primary screening of a matched antibody pair is performed according to antibody pairing for recognizing different epitopes.

Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and first shielding columns. The core layer includes an accommodating space, and the accommodating space has an inner side wall. The first shielding ring wall is disposed in the accommodating space and covers the inner side wall, in which the first shielding ring wall surrounds the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding columns are disposed in the first insulating layer.

Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and a plurality of shielding columns. The core layer has an accommodating space, in which the accommodating space has an inner sidewall. The electronic component is disposed in the accommodating space. The first shielding ring wall is disposed in the accommodating space and covers the inner sidewall, in which the first shielding ring wall surrounds the electronic component and is not in contact with the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The shielding columns are disposed in the first insulating layer.

Abstract: A slot cover and an integrated circuit access device having the slot cover are provided. The slot is used to be removably inserted into a slot of an electronic device and includes a frame, a positioning portion, an engaging portion, and at least one conductive elastic plate. The frame includes a center sheet, a first-side sheet configured to connect to an integrated circuit access module, and a second-side sheet. The first-side sheet and the second-side sheet are respectively located at a first side and a second side of the center sheet. The positioning portion and the engaging portion are respectively located above and below the center sheet. The at least one conductive elastic plate is disposed at the second-side sheet. When the slot cover is inserted in the slot of the electronic device, the center sheet blocks an opening of the slot.

Abstract: A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 ?m. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.

Abstract: A clothing-type fabric capable of heating itself and cooling itself for the bodily comfort of a wearer includes a fabric body, at least two first electrodes, a second electrode, and a processor. The fabric body includes an inner surface and an outer surface opposite to the inner surface. The at least two first electrodes are disposed above the inner surface and the outer surface. The first electrode disposed above the inner surface can sense a body temperature of a wearer (first temperature value). The first electrode disposed above the outer surface can sense temperature of ambient environment (second temperature value). The second electrode is disposed above the inner surface, and can release heat and absorb heat. The processor can receive the first and the second temperature values, and control the second electrode to release or absorb heat by reference to the first temperature value and the second temperature value.

Abstract: A stretchable sensing structure includes a stretchable sensing array, signal transmission lines, and a signal processing element. The stretchable sensing array includes at least two first sensing electrodes arranged in an array. The first sensing electrodes sense different physiological signals. Each first sensing electrode includes a first stretchable substrate layer, a pre-stretched pattern layer formed on the first stretchable substrate layer, and an electrode sheet formed on the first stretchable substrate layer and in electrical contact with the pre-stretched pattern layer. A material of the electrode sheet is carbon paste. The first sensing electrode senses different physiological signals. Two adjacent first sensing electrodes are electrically connected through the signal transmission line. The first sensing electrode is electrically connected to the signal processing element through the signal transmission line.

Abstract: A circuit board includes an insulating made by a low dielectric resin composition includes a low dielectric resin containing acid anhydride, an epoxy resin, polyphenylene ether resin with vinyl and active esters, maleic acid liquid polybutadiene, and an accelerator. Such low dielectric resin can be dissolved in organic solvent more easily than a low dielectric resin without acid anhydride, and the low dielectric resin containing acid anhydride has a better compatibility with other organic components than a low dielectric resin without acid anhydride. A low dielectric resin composition with lower dielectric constant and better properties can thus be obtained.