Abstract: A bendable sheath and a delivery system using the bendable sheath. The bendable sheath comprises a tube body (3). The tube body (3) comprises a distal end and a proximal end. A tube wall of the tube body (3) is connected to a pull wire (8). One end of the pull wire (8) extends towards the proximal end of the tube body (3), and the other end is connected to the tube body (3) near the distal end of the tube body (3). The pull wire (8) comprises at least a section thereof disposed freely outside the tube body (3) and near the distal end of the tube body (3). The pull wire (8) in the bendable sheath comprises the section disposed freely outside the sheath tube body (3) and, when pulled, the section is disposed so as to facilitate the application of force. The section moves relative to the tube body (3), such that a force application point is adaptively changed.

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

Abstract: A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass , and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).

Abstract: A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire (50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).

Abstract: Substrates, assemblies, and techniques for enabling multi-chip flip chip packages are disclosed herein. For example, in some embodiments, a package substrate may include a first side face; a second side face, wherein the second side face is opposite to the first side face along an axis; a portion of insulating material extending from the first side face to the second side face; wherein a cross-section of the portion of insulating material taken perpendicular to the axis has a stairstep profile. Solder pads may be disposed at base and step surfaces of the portion of insulating material. One or more dies may be coupled to the package substrate (e.g., to form a multi-chip flip chip package), and in some embodiments, additional IC packages may be coupled to the package substrate. In some embodiments, the package substrate may be reciprocally symmetric or approximately reciprocally symmetric.

Abstract: An apparatus is described that includes a semiconductor chip package. The semiconductor chip package includes a plurality of stacked semiconductor chips. The plurality of stacked semiconductor chips are stacked with a lateral offset, wherein, the lateral offset exposes first wirebond pads of the plurality of stacked semiconductor chips. The semiconductor chip package further includes a substrate interposer having second wirebond pads. The semiconductor chip package further includes wirebonds connecting the first wirebond pads and the second wirebond pads. The semiconductor chip package further includes a package substrate. The semiconductor chip package further includes vias that are electrically connected to the substrate interposer and a first surface of the package substrate. The semiconductor chip package further includes package level I/Os on a second surface of the package substrate that is opposite the first surface of the package substrate.

Abstract: Disclosed herein are integrated circuit (IC) die stacks, as well as related apparatuses and methods. For example, in some embodiments, an IC package may include: a package substrate having a substrate conductive contact; a first die coupled to the package substrate, wherein the first die has a first face and an opposing second face, the second face of the first die is between the first face of the first die and the package substrate, and the first die has a first conductive contact at the first face of the first die; a second die coupled to the first die, wherein the second die has a second conductive contact facing the first face of the first die; and a bondwire between the first conductive contact and the substrate conductive contact, wherein the bondwire is also in electrical contact with the second conductive contact.

Abstract: Techniques for providing an integrated circuit package that avoids or eliminates x-y area and z-height compared to conventional integrated circuit packages. In certain examples, an example package can utilize a substrate with an opening and bottom side or sidewall terminations to avoid adding addition x-y substrate area or z-axis package height associated with an integrated circuit die of a stack of integrated circuit dies of the package.

Abstract: Electronic device package technology is disclosed. An electronic device package can comprise a substrate. The electronic device package can also comprise first and second electronic components in a stacked configuration. Each of the first and second electronic components can include an electrical interconnect portion exposed toward the substrate. The electronic device package can further comprise a mold compound encapsulating the first and second electronic components. In addition, the electronic device package can comprise an electrically conductive post extending through the mold compound between the electrical interconnect portion of at least one of the first and second electronic components and the substrate. Associated systems and methods are also disclosed.

Abstract: Various examples disclosed relate to a substrate for a semiconductor. The substrate includes a first conducting layer, having a first surface and an opposite second surface. The substrate further includes a second conducting layer extending in a direction substantially parallel to the first conducting layer. The second conducting layer includes a third surface and an opposite fourth surface. A first dielectric layer is disposed between the second surface of the first conducting layer and the third surface of the second conducting layer. The first dielectric layer includes a first dielectric material and a fiber. Slots extends between the first conducting layer and the second conducting layer. Each of the slots is defined by an internal surface of the first conducting layer, the second conducting layer, and the first dielectric layer.

Abstract: In some forms, an electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a plurality of lobes projecting distally from a center of the ball pad. In some forms, he electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a lobe projecting distally from a center of the ball pad. In some forms, the electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes at least one lobe projecting distally from a center of the ball pad; and an electronic package that includes at least one conductor that electrically connects the ball pad on the substrate to the electronic package.

Abstract: A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire (50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).

Abstract: A package with improved solder joint reliability is disclosed. The package includes dummy beams with less rigidity and stiffness (relative to the die) that are placed in between the die and the substrate. The reduced rigidity and stiffness of the dummy beams significantly mitigates any die shadow effects on the solder joints. Also, because the die is attached to the dummy beams and does not directly contact the substrate itself, the die shadow effect from a rigid die is further reduced.

Abstract: Substrates, assemblies, and techniques for enabling multi-chip flip chip packages are disclosed herein. For example, in some embodiments, a package substrate may include a first side face; a second side face, wherein the second side face is opposite to the first side face along an axis; a portion of insulating material extending from the first side face to the second side face; wherein a cross-section of the portion of insulating material taken perpendicular to the axis has a stairstep profile. Solder pads may be disposed at base and step surfaces of the portion of insulating material. One or more dies may be coupled to the package substrate (e.g., to form a multi-chip flip chip package), and in some embodiments, additional IC packages may be coupled to the package substrate. In some embodiments, the package substrate may be reciprocally symmetric or approximately reciprocally symmetric.