Patents by Inventor Mao-Hsing Chiu

Mao-Hsing Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing metal oxide semiconductor transistor
    Patent number: 11756839
    Abstract: A method for manufacturing a MOS transistor includes following. A gate stack structure and a hardmask layer on the gate stack structure are sequentially formed on a substrate. A first spacer is formed on sidewalls of the gate stack structure and the hardmask layer. A photoresist layer is formed on a sidewall of the first spacer. A top surface of the photoresist layer is higher than a top surface of the gate stack structure. The hardmask layer and a portion of the first spacer are removed to expose the top surface of the gate stack structure. A top surface of a remaining first spacer is higher than the top surface of the gate stack structure. The photoresist layer is removed. A second spacer is formed on a sidewall of the remaining first spacer. A top surface of the second spacer is higher than the top surface of the gate stack.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: September 12, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wan-Yan Lin, Yu-Chieh Su, Ming-Chien Chiu, Mao-Hsing Chiu
  • METHOD FOR MANUFACTURING METAL OXIDE SEMICONDUCTOR TRANSISTOR
    Publication number: 20220216113
    Abstract: A method for manufacturing a MOS transistor includes following. A gate stack structure and a hardmask layer on the gate stack structure are sequentially formed on a substrate. A first spacer is formed on sidewalls of the gate stack structure and the hardmask layer. A photoresist layer is formed on a sidewall of the first spacer. A top surface of the photoresist layer is higher than a top surface of the gate stack structure. The hardmask layer and a portion of the first spacer are removed to expose the top surface of the gate stack structure. A top surface of a remaining first spacer is higher than the top surface of the gate stack structure. The photoresist layer is removed. A second spacer is formed on a sidewall of the remaining first spacer. A top surface of the second spacer is higher than the top surface of the gate stack.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 7, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wan-Yan Lin, Yu-Chieh Su, Ming-Chien Chiu, Mao-Hsing Chiu