Abstract: A timing controller adapted to a flat display includes a voltage detecting circuit, a clock generator, a first multiplexer and a second multiplexer. The voltage detecting circuit detects a variation of an operating voltage and thus outputs a reset signal. The clock generator outputs a start signal and a first clock signal. The first multiplexer is controlled by the reset signal and coupled to the start signal and a constant voltage. The second multiplexer is controlled by the reset signal and coupled to the first clock signal and a second clock signal. A frequency of the second clock signal is obviously higher than a frequency of the first clock signal.

Abstract: A gate driver for driving a display device is disclosed. The gate driver, which includes: a first input buffer configured to for receiving a reference voltage and outputting a first buffered voltage, a control circuit configured to for outputting a plurality of scan starting signals and compensating starting signals, a plurality of compensating output buffers, and a plurality of scan output buffers. Each of the plurality of compensating output buffers is configured to respectively receive one of the compensating starting signals and respectively output a compensating signal, wherein, each compensating output buffer receives the first buffered voltage as power. Each of the plurality of scanning output buffers is configured to respectively receive one of the scan starting signals and output a scan signal.

Abstract: A gate driver of a liquid crystal display includes classes of driving circuits coupled to each other for outputting gate pulses. At least one class of driving circuits includes a shift register and a switch. The shift register outputs the gate pulse corresponding to the class of driving circuit according to the gate pulse outputted by a former class of driving circuits. The switch controls the enable of the shift register according to the gate pulse outputted by the former class of driving circuit and the gate pulse outputted by the class of driving circuit.

Abstract: A gate driver for driving a display device is disclosed. The gate driver, which includes: a first input buffer configured to for receiving a reference voltage and outputting a first buffered voltage, a control circuit configured to for outputting a plurality of scan starting signals and compensating starting signals, a plurality of compensating output buffers, and a plurality of scan output buffers. Each of the plurality of compensating output buffers is configured to respectively receive one of the compensating starting signals and respectively output a compensating signal, wherein, each compensating output buffer receives the first buffered voltage as power. Each of the plurality of scanning output buffers is configured to respectively receive one of the scan starting signals and output a scan signal.

Abstract: A level shift circuit adds two NMOS transistors or two PMOS transistors between the NMOS transistors and PMOS transistors at the VP-side and the VN-side and connects the gates of the added transistors to the two output terminals. By this architecture, the level shift circuit of the present invention can successfully convert a small input voltage into a large output voltage with less DC current and/or without any additional bandgap circuit.

Abstract: A timing controller adapted to a flat display includes a voltage detecting circuit, a clock generator, a first multiplexer and a second multiplexer. The voltage detecting circuit detects a variation of an operating voltage and thus outputs a reset signal. The clock generator outputs a start signal and a first clock signal. The first multiplexer is controlled by the reset signal and coupled to the start signal and a constant voltage. The second multiplexer is controlled by the reset signal and coupled to the first clock signal and a second clock signal. A frequency of the second clock signal is obviously higher than a frequency of the first clock signal.

Abstract: A level shift circuit adds two NMOS transistors or two PMOS transistors between the NMOS transistors and PMOS transistors at the VP-side and the VN-side and connects the gates of the added transistors to the two output terminals. By this architecture, the level shift circuit of the present invention can successfully convert a small input voltage into a large output voltage with less DC current and/or without any additional bandgap circuit.

Abstract: A gate driver of a liquid crystal display includes classes of driving circuits coupled to each other for outputting gate pulses. At least one class of driving circuits includes a shift register and a switch. The shift register outputs the gate pulse corresponding to the class of driving circuit according to the gate pulse outputted by a former class of driving circuits. The switch controls the enable of the shift register according to the gate pulse outputted by the former class of driving circuit and the gate pulse outputted by the class of driving circuit.

Abstract: A method of forming a high polysilicon resistor over a dielectric layer, comprising the following steps. A polysilicon resistor over a semiconductor structure is provided. The polysilicon resistor has a doped polysilicon layer having a first voltage coefficient of resistance and grain boundaries having a first trapping density. A to a first level of DC current is provided for a predetermined duration through the doped polysilicon layer to stress the doped polysilicon layer to partially melt the doped polysilicon layer without causing breakdown of the doped polysilicon layer. The to a first level of DC current is removed to allow recrystallization of the melted doped polysilicon layer, whereby the recrystallized doped polysilicon layer has a second voltage coefficient of resistance less than the first voltage coefficient of resistance and grain boundaries having a second trapping density that is less than the first trapping density. This makes the Rs of the polysilicon to be stable and saturated.