Patents by Inventor Mao-Hsuan Chou
Mao-Hsuan Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250147086Abstract: The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is ? times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.Type: ApplicationFiled: January 13, 2025Publication date: May 8, 2025Inventors: MAO-HSUAN CHOU, RUEY-BIN SHEEN, CHIH-HSIEN CHANG
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Patent number: 12228598Abstract: The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is ? times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.Type: GrantFiled: July 20, 2022Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Mao-Hsuan Chou, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 12149264Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.Type: GrantFiled: June 6, 2023Date of Patent: November 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 11984901Abstract: A counter signal counting at a frequency of a clock signal is generated. Among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio is selected. In response to the counter signal reaching the selected threshold, a logic level of an output signal is switched.Type: GrantFiled: May 31, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen
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Publication number: 20240027504Abstract: The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is ? times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Inventors: MAO-HSUAN CHOU, RUEY-BIN SHEEN, CHIH-HSIEN CHANG
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Publication number: 20230318617Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.Type: ApplicationFiled: June 6, 2023Publication date: October 5, 2023Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 11689214Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.Type: GrantFiled: May 24, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 11664793Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.Type: GrantFiled: January 7, 2022Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 11555842Abstract: A system, a method and a built-in phase noise measurement apparatus are introduced. The built-in phase noise measurement apparatus includes a first DLL and a TDC, in which the first DLL circuit controls a delay of a first signal to generate a second signal based on a control code, tune the control code until a phase of the second signal is aligned to a phase of a reference clock signal, and record a value of the control code when the phase of the second signal is aligned to the phase of the reference clock signal. The DLL circuit controls the delay of the first signal based on the value of the control code after the phase of the second signal is aligned to the phase of the reference clock signal. The TDC determines the phase noise of the first signal based on the reference clock signal and the second signal.Type: GrantFiled: September 11, 2020Date of Patent: January 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen, Ya-Tin Chang
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Patent number: 11555851Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).Type: GrantFiled: May 4, 2022Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20220294460Abstract: A counter signal counting at a frequency of a clock signal is generated. Among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio is selected. In response to the counter signal reaching the selected threshold, a logic level of an output signal is switched.Type: ApplicationFiled: May 31, 2022Publication date: September 15, 2022Inventors: Mao-Hsuan CHOU, Chih-Hsien CHANG, Ruey-Bin SHEEN
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Publication number: 20220286141Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20220260634Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Inventors: Mao-Hsuan CHOU, Ya-Tin CHANG, Ruey-Bin SHEEN, Chih-Hsien CHANG
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Patent number: 11374584Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle lower than 50% and greater than 1/r, where r is the frequency ratio.Type: GrantFiled: February 9, 2021Date of Patent: June 28, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mao-Hsuan Chou, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 11356115Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.Type: GrantFiled: December 4, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 11333708Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).Type: GrantFiled: February 19, 2021Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20220131536Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.Type: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Inventors: Mao-Hsuan CHOU, Ya-Tin CHANG, Ruey-Bin SHEEN, Chih-Hsien CHANG
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Publication number: 20220082602Abstract: A system, a method and a built-in phase noise measurement apparatus are introduced. The built-in phase noise measurement apparatus includes a first DLL and a TDC, in which the first DLL circuit controls a delay of a first signal to generate a second signal based on a control code, tune the control code until a phase of the second signal is aligned to a phase of a reference clock signal, and record a value of the control code when the phase of the second signal is aligned to the phase of the reference clock signal. The DLL circuit controls the delay of the first signal based on the value of the control code after the phase of the second signal is aligned to the phase of the reference clock signal. The TDC determines the phase noise of the first signal based on the reference clock signal and the second signal.Type: ApplicationFiled: September 11, 2020Publication date: March 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen, Ya-Tin Chang
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Patent number: 11228304Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.Type: GrantFiled: November 19, 2020Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20210250041Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.Type: ApplicationFiled: December 4, 2020Publication date: August 12, 2021Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang