Patents by Inventor Mao Lee
Mao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11961637Abstract: This disclosure relates to a stretchable composite electrode and a fabricating method thereof, and particularly relates to a stretchable composite electrode including a silver nanowire layer and a flexible polymer film and a fabricating method thereof.Type: GrantFiled: December 7, 2022Date of Patent: April 16, 2024Assignee: TPK ADVANCED SOLUTIONS INC.Inventors: Wei Sheng Chen, Ching Mao Huang, Jia Hui Zhou, Huan Ran Yu, Shu Xiong Wang, Chin Hui Lee
-
Patent number: 11956541Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.Type: GrantFiled: January 26, 2023Date of Patent: April 9, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chen-Hsien Fan, Sung-Mao Tsai, Yueh-Lin Lee, Yu-Chiao Lo, Mao-Kuo Hsu, Ching-Chieh Huan, Yi-Chun Cheng
-
Patent number: 11934034Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, a driving assembly, and an assist assembly. The movable portion is used for connecting to an optical element having a main axis. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The assist assembly limits the movement of the movable portion relative to the fixed portion.Type: GrantFiled: April 8, 2020Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chen-Hsien Fan, Yueh-Lin Lee, Yu-Chiao Lo, Sung-Mao Tsai, Shang-Hung Chen
-
Patent number: 11924039Abstract: Provided are a system and a method for optimization of network function management and computer readable medium thereof that develop an OAM system architecture compatible with a standard MANO framework set by ETSI, so as to effectively integrate and manage the resources and situation configurations of the network elements (including VNF and CNF) of different manufacturers. Therefore, containment management for various network elements may be flexibly integrated, advantages of the standard MANO framework may be preserved, cost for customized development of various OAM systems and the information transmission therefrom may be reduced, and overall efficiency is increased.Type: GrantFiled: September 23, 2022Date of Patent: March 5, 2024Assignee: CHUNGHWA TELECOM CO., LTD.Inventors: Yuan-Mao Hung, Mao-Yao Lee, Chien-Hua Lee, Shih-Che Chien
-
Patent number: 11914169Abstract: An optical member driving mechanism is provided. The optical member driving mechanism is configured to hold an optical member and drive the optical member to move. The optical member driving mechanism includes a first movable portion, a fixed portion, and a driving assembly. The first movable portion is movable relative to the fixed portion. The driving assembly is configured to drive the first movable portion to move relative to the fixed portion.Type: GrantFiled: January 24, 2020Date of Patent: February 27, 2024Assignee: TDK TAIWAN CORP.Inventors: Chen-Hsien Fan, Sung-Mao Tsai, Chia-Che Wu, Yueh-Lin Lee
-
Publication number: 20230411496Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.Type: ApplicationFiled: May 23, 2022Publication date: December 21, 2023Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Yi-Ning TAI, Hong-Mao LEE, Yan-Ming TSAI, Wei-Yip LOH, Harry CHIEN, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
-
Publication number: 20230411242Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kan-Ju LIN, Lin-Yu HUANG, Min-Hsuan LU, Wei-Yip LOH, Hong-Mao LEE, Harry CHIEN
-
Publication number: 20230402366Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.Type: ApplicationFiled: June 9, 2022Publication date: December 14, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Kuan-Kan HU, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN
-
Publication number: 20230402278Abstract: A method of forming a semiconductor device includes following operations. A substrate is provided with a gate stack thereon, an epitaxial layer therein, and a dielectric layer aside the gate stack and over the epitaxial layer. An opening is formed through the dielectric layer, and the opening exposes the epitaxial layer. A metal silicon-germanide layer is formed on the epitaxial layer, wherein the metal silicon-germanide layer includes a metal having a melting point of about 1700° C. or higher. A connector is formed over the metal silicon-germanide layer in the opening.Type: ApplicationFiled: June 12, 2022Publication date: December 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Ming Tsai, Wei-Yip Loh, Harry CHIEN, Chih-Shiun Chou, Hong-Mao Lee, Chih-Wei Chang, Ming-Hsing Tsai
-
Publication number: 20230386918Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
-
Publication number: 20230387316Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin LIANG, Min-Chiang CHUANG, Chia-Cheng CHEN, Chun-Hung WU, Liang-Yin CHEN, Sung-Li WANG, Pinyen LIN, Kuan-Kan HU, Jhih-Rong HUANG, Szu-Hsian LEE, Tsun-Jen CHAN, Cheng-Wei LIAN, Po-Chin CHANG, Chuan-Hui SHEN, Lin-Yu HUANG, Yuting CHENG, Yan-Ming TSAI, Hong-Mao LEE
-
Patent number: 11791208Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.Type: GrantFiled: January 21, 2022Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
-
Publication number: 20230230916Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.Type: ApplicationFiled: January 18, 2022Publication date: July 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN
-
Publication number: 20220375863Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.Type: ApplicationFiled: July 26, 2022Publication date: November 24, 2022Inventors: Pin-Wen CHEN, Mei-Hui FU, Hong-Mao LEE, Wei-Jung LIN, Chih-Wei CHANG
-
Publication number: 20220367667Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
-
Patent number: 11503611Abstract: A method for allocating wireless resources for a number of user equipment in a wireless communication system is applied in an apparatus. The apparatus collects the traffic demands of all the user equipment and then selects a beam based on the traffic demands of all the user equipment in every time slot to make better utilization of resource blocks.Type: GrantFiled: August 26, 2020Date of Patent: November 15, 2022Assignee: HON LIN TECHNOLOGY CO., LTD.Inventors: Ching-Ju Lin, Yu-Hsuan Liu, Chi-Mao Lee, Ping-Jung Hsieh, Tun-Yu Yu, Ming-Yu Lee
-
Patent number: 11482495Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.Type: GrantFiled: November 13, 2019Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, ltd.Inventors: Pin-Wen Chen, Mei-Hui Fu, Hong-Mao Lee, Wei-Jung Lin, Chih-Wei Chang
-
Patent number: 11444028Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: GrantFiled: December 16, 2019Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
-
Patent number: 11411094Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.Type: GrantFiled: January 13, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
-
Publication number: 20220148920Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.Type: ApplicationFiled: January 21, 2022Publication date: May 12, 2022Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin