Patents by Inventor Mao Lin Hsu

Mao Lin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145470
    Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Lung-Kun CHU, Mao-Lin HUANG, Chung-Wei HSU, Jia-Ni YU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 11961840
    Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240120402
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
  • Publication number: 20240113195
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11948987
    Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240096880
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 21, 2024
    Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
  • Patent number: 11927799
    Abstract: A data transmission system is disclosed. The data transmission system includes at least one signal processing device, at least one conversion device, at least one antenna device, and at least one flexible printed circuit board. The at least one signal processing device is configured to generate or receive at least one data. The at least one conversion device is configured to transform between the at least one data and an optical signal. The at least one antenna device is configured to obtain the at least one data according to the optical signal, and configured to receive or transmit the at least one data wirelessly. The at least one flexible printed circuit board includes at least one conductive layer and at least one optical waveguide layer. The at least one optical waveguide layer is configured to transmit the optical signal.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 12, 2024
    Inventors: Po-Kuan Shen, Chun-Chiang Yen, Chiu-Lin Yu, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu, Chao-Chieh Hsu
  • Patent number: 7371524
    Abstract: The present invention relates to marker components, fluorescent probes, oligonucleotides, hybridization assays, and immunoassays using such products, and methods for making such products. According to the present invention, detectably labeled marker components are provided that comprise a fluorescent moiety coupled to two small solubilizing groups, one on each side of the molecular plane, said fluorescent moiety having substituents to control net charge so as to reduce or remove the problems of solvent sensitivity and nonspecific binding.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: May 13, 2008
    Inventors: Walter B. Dandliker, Mao Lin Hsu, William P. Murphy, Jr.
  • Patent number: 5919922
    Abstract: Fluorescent dyes which are free of aggregation and serum binding are provided. These dyes are suitable for applications such as fluorescence immunoassays, in vivo imaging and in vivo tumor therapy.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: July 6, 1999
    Assignee: Hyperion, Inc.
    Inventors: Walter Beach Dandliker, Mao-Lin Hsu
  • Patent number: 5880287
    Abstract: Fluorescent dyes which are free of aggregation and serum binding are provided. These dyes are suitable for applications such as fluorescence immunoassays, in vivo imaging and in vivo tumor therapy. Fluorescence immunoassays methods are provided which use fluorescent dyes which are free of aggregation and serum binding. Such immunoassay methods are thus, particularly useful for the assay of biological fluids, such as serum, plasma, whole blood and urine. The present invention is directed to compositions comprising an oligonucleotide linked to a detectably labeled marker component comprising a fluorophore moiety which comprises a substantially planar, multidentate macrocyclic ligand coordinated to a central atom capable of coordinating with two axial ligands and two polyoxyhydrocarbyl moieties which are attached as axial ligands to the central atom. The present invention is also directed to nucleic acid hybridization and amplification methods employing such compositions.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 9, 1999
    Assignee: Hyperion, Inc.
    Inventors: Walter B. Dandliker, Robert Francis Devlin, Peter Olaf Gustaf Arrhenius, Mao-Lin Hsu
  • Patent number: 5641878
    Abstract: Fluorescent dyes which are free of aggregation and serum binding are provided. These dyes are suitable for applications such as fluorescence immunoassays, in vivo imaging and in vivo tumor therapy. The dyes are particularly useful in fluorescence immunoassays of biological samples containing serum. Such dyes have two polyoxyhydrocarbyl moities, one located on either side of a planar molecular structure such as a porphyrin derivative, azaporphyrin derivative, corrin derivative, sapphyrin derivative or porphycene derivative.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: June 24, 1997
    Assignee: Diatron Corporation
    Inventors: Walter B. Dandliker, Mao-Lin Hsu