Patents by Inventor Mao-Nan Wang
Mao-Nan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071956Abstract: Semiconductor structures and methods for forming the same are provided. A method according to the present disclosure includes forming active regions on a substrate, forming an interconnect structure over the active regions, the interconnect structure including a plurality of dielectric layers and a guard ring disposed within the dielectric layers, etching an opening through the interconnect structure and at least a first portion of the active regions, the opening extending into the substrate, and forming a via structure within the opening. The via structure is surrounded by the guard ring when viewed along a direction perpendicular to a top surface of the substrate.Type: ApplicationFiled: April 21, 2023Publication date: February 29, 2024Inventors: Chih Hsin YANG, Yen Lian LAI, Dian-Hau CHEN, Mao-Nan WANG
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Publication number: 20230395487Abstract: Passive devices are provided. In an embodiment, a passive device includes a substrate comprising a first region and a second region, a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively, a first vertical stack of conductive features disposed over the first region, a metal-insulator-metal (MIM) capacitor disposed over the second region and comprising a vertical stack of conductor plates, a first contact via extending through the first vertical stack of conductive features and electrically coupled to the first lower contact feature, and a second contact via extending through a portion of the vertical stack of conductor plates and electrically coupled to the second lower contact feature. A number of conductive features penetrated by the first contact via is different than a number of conductor plates penetrated by the second contact via.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Inventors: Mao-Nan Wang, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen
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Publication number: 20230352394Abstract: A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than ?0.3 GPa.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Te CHU, Yuan-Yang HSIAO, Chih-Pin CHIU, Ying-Yao LAI, Mao-Nan WANG, Chen-Chiu HUANG, Dian-Hau CHEN
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Publication number: 20230317631Abstract: Methods for forming a back-end-of-line (BEOL) passive device structure are provided. A method according to the present disclosure includes depositing a first conductor layer over a substrate, patterning the first conductor layer to form a patterned first conductor layer, depositing a first insulation layer over the patterned first conductor layer, depositing a second conductor layer over the first insulation layer, patterning the second conductor layer to form a patterned second conductor layer, depositing a second insulation layer over the patterned second conductor layer, depositing a third conductor layer over the second insulation layer, and patterning the third conductor layer to form a patterned third conductor layer. The patterning of the first conductor layer includes removing a right-angle edge of the first conductor layer.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventors: Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Wen-Chiung Tu, Ying-Yao Lai, Chen-Te Chu, Mao-Nan Wang, Chen-Chiu Huang, Dian-Hau Chen
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Publication number: 20220359438Abstract: A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Fan HUANG, Mao-Nan WANG, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
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Patent number: 11437331Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.Type: GrantFiled: October 17, 2019Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Mao-Nan Wang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11222857Abstract: In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.Type: GrantFiled: February 24, 2020Date of Patent: January 11, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Fan Huang, Dian-Hau Chen, Mao-Nan Wang, Tzu-Li Lee, Yen-Ming Chen, Tzung-Luen Li
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Patent number: 11189538Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.Type: GrantFiled: May 14, 2019Date of Patent: November 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Mao-Nan Wang, Kuo-Chin Chang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20210265291Abstract: In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Inventors: Chih-Fan Huang, Dian-Hau Chen, Mao-Nan Wang, Tzu-Li Lee, Yen-Ming Chen, Tzung-Luen Li
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Publication number: 20210118829Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Fan HUANG, Mao-Nan WANG, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
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Publication number: 20200105634Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.Type: ApplicationFiled: May 14, 2019Publication date: April 2, 2020Inventors: Chih-Fan Huang, Mao-Nan Wang, Kuo-Chin Chang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 9893191Abstract: A semiconductor device having a u-shaped FinFET and methods of forming the same are disclosed. The semiconductor device includes a substrate and a fin over the substrate, wherein the fin has a u-shape from a top view with first and second arm portions and a bridge portion connecting the first and second arm portions. The semiconductor device further includes a first gate over the substrate, engaging the fin at both the first and second arm portions and the bridge portion. A source region of the FinFET is formed in the first arm portion, a drain region of the FinFET is formed in the second arm portion, and a channel region of the FinFET is formed in the fin between the source region and the drain region.Type: GrantFiled: August 20, 2014Date of Patent: February 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yao Wen, Mao-Nan Wang, Sai-Hooi Yeong
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Publication number: 20160056295Abstract: A semiconductor device having a u-shaped FinFET and methods of forming the same are disclosed. The semiconductor device includes a substrate and a fin over the substrate, wherein the fin has a u-shape from a top view with first and second arm portions and a bridge portion connecting the first and second arm portions. The semiconductor device further includes a first gate over the substrate, engaging the fin at both the first and second arm portions and the bridge portion. A source region of the FinFET is formed in the first arm portion, a drain region of the FinFET is formed in the second arm portion, and a channel region of the FinFET is formed in the fin between the source region and the drain region.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Inventors: Tsung-Yao Wen, Mao-Nan Wang, Sai-Hooi Yeong