Patents by Inventor Mao-Yi Chang

Mao-Yi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10630319
    Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 21, 2020
    Assignee: MEDIATEK INC.
    Inventors: Ju-Ya Chen, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Mao-Ching Chiu, Timothy Perrin Fisher-Jeffes, Chong-You Lee
  • Publication number: 20200091114
    Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo Lung Pan, Tin-Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Patent number: 10581457
    Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 3, 2020
    Assignee: MEDIATEK INC.
    Inventors: Mao-Ching Chiu, Timothy Perrin Fisher-Jeffes, Chong-You Lee, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Patent number: 10567116
    Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 18, 2020
    Assignee: MEDIATEK INC.
    Inventors: Mao-Ching Chiu, Chong-You Lee, Timothy Perrin Fisher-Jeffes, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Publication number: 20190372600
    Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Inventors: Wei-Jen Chen, Ju-Ya Chen, Yen-Shuo Chang, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Cheng-Yi Hsu, Chong-You Lee
  • Patent number: 10461023
    Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Yen Chang, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Tzung-Hui Lee, Teng-Yuan Lo, Hao-Chun Ting
  • Patent number: 10432227
    Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 1, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wei-Jen Chen, Ju-Ya Chen, Yen-Shuo Chang, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Cheng-Yi Hsu, Chong-You Lee
  • Patent number: 8314898
    Abstract: A display device includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a passivation layer covering the switching device and the capacitor, and a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings exposing the contact pads.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 20, 2012
    Assignee: AU Optronics Corp.
    Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
  • Patent number: 7994511
    Abstract: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: August 9, 2011
    Assignee: Au Optronics Corp.
    Inventors: Chih-Wei Chao, Mao-Yi Chang
  • Publication number: 20110164195
    Abstract: A display device includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a passivation layer covering the switching device and the capacitor, and a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings exposing the contact pads.
    Type: Application
    Filed: March 18, 2011
    Publication date: July 7, 2011
    Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
  • Patent number: 7932987
    Abstract: An LCD includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a bridge electrode formed in the first opening, a passivation layer covering the switching device and the capacitor, a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device, a second substrate having a common electrode disposed on the first substrate, and a liquid crystal layer. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings respectively exposing the contact pads and the bridge electrode, wherein the bridge electrode is electrically disconnected from the contact pads.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: April 26, 2011
    Assignee: AU Optronics Corp.
    Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
  • Publication number: 20100182559
    Abstract: An LCD includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a bridge electrode formed in the first opening, a passivation layer covering the switching device and the capacitor, a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device, a second substrate having a common electrode disposed on the first substrate, and a liquid crystal layer. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings respectively exposing the contact pads and the bridge electrode, wherein the bridge electrode is electrically disconnected from the contact pads.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 22, 2010
    Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
  • Patent number: 7755738
    Abstract: An LCD device has an LCD panel having a peripheral region, a heating layer disposed on the LCD panel, and two first flexible printed circuits (FPCs) electrically connected to the heating layer, and adapted to transmit voltage to the heating layer so that the heating layer can generate heat. At least one of the FPCs has a wide portion and a narrow portion being fixed in the peripheral region of the LCD panel and being connected to the heating layer.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: July 13, 2010
    Assignee: AU Optronics Corp.
    Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
  • Patent number: 7649206
    Abstract: A sequential lateral solidification (SLS) mask comprises a plurality of parallelizing repeat patterns. Each of the patterns further comprises a major symmetrical axis and a short axis, and each of the patterns is also composed of first units and second units, in which both the first unit and the second unit comprise respectively a plurality of light transmitting portions and light absorption portions. The first units are positioned in mirror symmetry to the second units via the major symmetrical axis.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: January 19, 2010
    Assignee: AU Optronics Corp.
    Inventors: Mao-Yi Chang, Chih-Hsiung Chang
  • Publication number: 20090127554
    Abstract: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.
    Type: Application
    Filed: December 9, 2008
    Publication date: May 21, 2009
    Inventors: Chih-Wei Chao, Mao-Yi Chang
  • Patent number: 7476601
    Abstract: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: January 13, 2009
    Assignee: A U Optronics Corp.
    Inventors: Chih-Wei Chao, Mao-Yi Chang
  • Publication number: 20080316416
    Abstract: An LCD device has an LCD panel having a peripheral region, a heating layer disposed on the LCD panel, and two first flexible printed circuits (FPCs) electrically connected to the heating layer, and adapted to transmit voltage to the heating layer so that the heating layer can generate heat. At least one of the FPCs has a wide portion and a narrow portion being fixed in the peripheral region of the LCD panel and being connected to the heating layer.
    Type: Application
    Filed: August 17, 2007
    Publication date: December 25, 2008
    Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
  • Patent number: 7425349
    Abstract: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings is formed in the second metal layer. A silicon layer is formed on the second metal layer; a silicon seed is formed on the substrate inside each of the holes. After removing the first and the second metal layers, an amorphous silicon layer is formed on the substrate by using the silicon seed. Then a laser crystallization step is performed to form a polysilicon layer from the amorphous layer. Since the position of the silicon seed can be controlled, the size and distribution of the silicon grain and the number of the silicon crystal interface can also be controlled.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: September 16, 2008
    Assignee: Au Optronics Corporation
    Inventors: Chien-Shen Wung, Mao-Yi Chang, Chih-Chin Chang
  • Patent number: 7393734
    Abstract: Method of fabricating polysilicon film includes forming insulating layer, first amorphous silicon layer, and cap layer over a substrate. An annealing is performed to transform the first amorphous silicon layer into first polysilicon layer with at least a hole. The cap layer is removed. A portion of the insulating layer within the hole is removed to form first opening within the insulating layer. The hole and the first opening constitute a second opening. A dielectric layer is formed over the first polysilicon layer. The dielectric layer also fills the second opening, causing a recess on the dielectric layer above the second opening. A second amorphous silicon layer is formed over the dielectric layer. A second annealing is performed to transform the second amorphous silicon layer into a second polysilicon layer. The second opening induces a thermal difference so as to cause a crystallizing direction for the second amorphous silicon layer.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: July 1, 2008
    Assignee: Au Optronics Corporation
    Inventor: Mao-Yi Chang
  • Patent number: 7303786
    Abstract: In a method of forming a polysilicon layer on a substrate, a first embodiment comprises: doping inert gas into the substrate to form a plurality of pores in the substrate; depositing a buffer later on the substrate; depositing an amorphous silicon layer on the buffer layer; and heating the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer. A second embodiment comprises: depositing a first buffer layer on a substrate; doping inert gas into the first buffer layer to form a plurality of pores in the first buffer layer; depositing a second buffer layer on the first buffer layer; depositing an amorphous silicon layer on the second buffer layer; and heating the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: December 4, 2007
    Assignee: AU Optronics Corp.
    Inventor: Mao-Yi Chang