Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A display device includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a passivation layer covering the switching device and the capacitor, and a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings exposing the contact pads.

Abstract: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.

Abstract: A display device includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a passivation layer covering the switching device and the capacitor, and a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings exposing the contact pads.

Abstract: An LCD includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a bridge electrode formed in the first opening, a passivation layer covering the switching device and the capacitor, a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device, a second substrate having a common electrode disposed on the first substrate, and a liquid crystal layer. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings respectively exposing the contact pads and the bridge electrode, wherein the bridge electrode is electrically disconnected from the contact pads.

Abstract: An LCD includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a bridge electrode formed in the first opening, a passivation layer covering the switching device and the capacitor, a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device, a second substrate having a common electrode disposed on the first substrate, and a liquid crystal layer. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings respectively exposing the contact pads and the bridge electrode, wherein the bridge electrode is electrically disconnected from the contact pads.

Abstract: An LCD device has an LCD panel having a peripheral region, a heating layer disposed on the LCD panel, and two first flexible printed circuits (FPCs) electrically connected to the heating layer, and adapted to transmit voltage to the heating layer so that the heating layer can generate heat. At least one of the FPCs has a wide portion and a narrow portion being fixed in the peripheral region of the LCD panel and being connected to the heating layer.

Abstract: A sequential lateral solidification (SLS) mask comprises a plurality of parallelizing repeat patterns. Each of the patterns further comprises a major symmetrical axis and a short axis, and each of the patterns is also composed of first units and second units, in which both the first unit and the second unit comprise respectively a plurality of light transmitting portions and light absorption portions. The first units are positioned in mirror symmetry to the second units via the major symmetrical axis.

Abstract: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.

Abstract: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.

Abstract: An LCD device has an LCD panel having a peripheral region, a heating layer disposed on the LCD panel, and two first flexible printed circuits (FPCs) electrically connected to the heating layer, and adapted to transmit voltage to the heating layer so that the heating layer can generate heat. At least one of the FPCs has a wide portion and a narrow portion being fixed in the peripheral region of the LCD panel and being connected to the heating layer.

Abstract: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings is formed in the second metal layer. A silicon layer is formed on the second metal layer; a silicon seed is formed on the substrate inside each of the holes. After removing the first and the second metal layers, an amorphous silicon layer is formed on the substrate by using the silicon seed. Then a laser crystallization step is performed to form a polysilicon layer from the amorphous layer. Since the position of the silicon seed can be controlled, the size and distribution of the silicon grain and the number of the silicon crystal interface can also be controlled.

Abstract: Method of fabricating polysilicon film includes forming insulating layer, first amorphous silicon layer, and cap layer over a substrate. An annealing is performed to transform the first amorphous silicon layer into first polysilicon layer with at least a hole. The cap layer is removed. A portion of the insulating layer within the hole is removed to form first opening within the insulating layer. The hole and the first opening constitute a second opening. A dielectric layer is formed over the first polysilicon layer. The dielectric layer also fills the second opening, causing a recess on the dielectric layer above the second opening. A second amorphous silicon layer is formed over the dielectric layer. A second annealing is performed to transform the second amorphous silicon layer into a second polysilicon layer. The second opening induces a thermal difference so as to cause a crystallizing direction for the second amorphous silicon layer.

Abstract: In a method of forming a polysilicon layer on a substrate, a first embodiment comprises: doping inert gas into the substrate to form a plurality of pores in the substrate; depositing a buffer later on the substrate; depositing an amorphous silicon layer on the buffer layer; and heating the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer. A second embodiment comprises: depositing a first buffer layer on a substrate; doping inert gas into the first buffer layer to form a plurality of pores in the first buffer layer; depositing a second buffer layer on the first buffer layer; depositing an amorphous silicon layer on the second buffer layer; and heating the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer.

Abstract: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings is formed in the second metal layer. A silicon layer is formed on the second metal layer; a silicon seed is formed on the substrate inside each of the holes. After removing the first and the second metal layers, an amorphous silicon layer is formed on the substrate by using the silicon seed. Then a laser crystallization step is performed to form a polysilicon layer from the amorphous layer. Since the position of the silicon seed can be controlled, the size and distribution of the silicon grain and the number of the silicon crystal interface can also be controlled.

Abstract: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings is formed in the second metal layer. A silicon layer is formed on the second metal layer; a silicon seed is formed on the substrate inside each of the holes. After removing the first and the second metal layers, an amorphous silicon layer is formed on the substrate by using the silicon seed. Then a laser crystallization step is performed to form a polysilicon layer from the amorphous layer. Since the position of the silicon seed can be controlled, the size and distribution of the silicon grain and the number of the silicon crystal interface can also be controlled.

Abstract: A method of manufacturing nano crystals disclosed herein is applicable to the fabrications of memory device and solar cell. The method of manufacturing nano crystals at least comprises steps of: providing a substrate with a thin film formed thereon, and transforming the thin film into the nano crystals by laser annealing, wherein a thickness of the thin film is equal to or less than about 50 ?, and a wavelength of the laser selected for laser annealing is equal to or less than about 500 nm.

Abstract: A sequential lateral solidification (SLS) mask comprises a plurality of parallelizing repeat patterns. Each of the patterns further comprises a major symmetrical axis and a short axis, and each of the patterns is also composed of first units and second units, in which both the first unit and the second unit comprise respectively a plurality of light transmitting portions and light absorption portions. The first units are positioned in mirror symmetry to the second units via the major symmetrical axis.