Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Abstract: A chip includes pads having first connecting surfaces, and conductive structures located on the first connecting surfaces. The conductive structures are disposed on the first connecting surfaces. Each of the conductive structures includes first metal layer, second metal layer, and third metal layer. The first metal layer connects one of the pads, and the second metal layer is disposed between the first metal layer and the third metal layer. On every pad, the first metal layer, the second metal layer, and the third metal layer are stacked along first direction on the first connecting surface of the pad, and the first direction is parallel to normal direction of the first connecting surface, and the first metal layer is made of material comprising gold, and the second metal layer is made of material comprising nickel. A wafer is also provided.

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Abstract: The present disclosure provides an interconnect structure. The interconnect structure includes a first connecting line, a second connecting line disposed over the first connecting line, and a connecting via disposed in a dielectric structure between the first connecting line and the second connecting line, and electrically connecting the first connecting line and the second connecting line. The connecting via includes a head portion and a body portion, and a width of the head portion is greater than a width of the body portion.

Abstract: The present disclosure provides a method for preparing an interconnect structure. One aspect of the present disclosure provides a method for preparing an interconnect structure. The method includes the following steps. A first dielectric layer is provided over a first connecting line. A first upper via opening is formed in the first dielectric layer, wherein the first upper via opening has a first width. A first lower via opening is formed in the first dielectric layer, wherein the first lower via opening is formed under and coupled to the first upper via opening. The first lower via opening has a second width less than the first width of the first upper via opening. A connecting via is formed in the first upper via opening and the first lower via opening. A second connecting line is formed over the connecting via.

Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a multilayer component, at least one contact pad, a passivation layer, a dielectric layer, and a metallic layer. The contact pad is disposed on the multilayer component, the passivation layer covers the multilayer component and the contact pad, and the dielectric layer is disposed on the passivation layer. The metallic layer penetrates through the dielectric layer and the passivation layer and is connected to the contact pad, and the metallic layer discretely tapers at positions of decreasing distance from the contact pad.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.

Abstract: The present disclosure provides a packaged semiconductor device and a method for preparing the same. The packaged semiconductor device includes a chip having a conductive pad; a first insulating layer disposed on the chip; a second insulating layer disposed on the first insulating layer; a conductive film disposed on the second insulating layer, a redistribution layer disposed on the conductive film; a probe pad disposed on the redistribution layer; and a third insulating, layer disposed on the redistribution layer and the second insulating layer, wherein the third insulating layer covers a portion of the probe pad, and there is no undercut at a region between the redistribution layer and the probe pad. The size of the probe pad is not limited by the undercut, as the size of the probe pad needs to be reduced in order to meet the requirement of continuous minimization of chip size.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.

Abstract: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate.

Abstract: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.