Abstract: The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a stack, active structures connecting structures and isolation layers. The stack is disposed on the substrate. The active structures penetrate through the stack in sub-array regions thereof. A plurality of memory cells are defined by cross points of gate electrodes in the stack and the active structures. The connecting structures penetrate through the stack between the sub-array regions. Each connecting structure includes a first portion, a second portion and a third portion. The first portion is formed as an outermost layer of the connecting structure and formed of polysilicon. The second portion is disposed in a space defined by the first portion and formed of amorphous silicon. The third portion is disposed on the second portion and formed of amorphous silicon. The isolation layers are disposed between sidewalls of the stack and the connecting structures.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a conductive pillar having a sidewall and a multi-layer isolation structure on the sidewall of the conductive pillar. The multi-layer isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is between the conductive pillar and the second isolation layer. The first isolation layer includes protrusions extending toward the second isolation layer. A density of the first isolation layer is different from that of the second isolation layer.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region has complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an oxide layer on the N-type doped poly silicon layer, and a conductive layer on the oxide layer. The array region includes gate structures and insulating layers alternately stacked on the conductive layer. A bottommost gate structure and the conductive layer together serve as ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4. The array region further includes a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region includes a plurality of complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an insulating layer on the N-type doped poly silicon layer; and a P-type doped poly silicon layer on the insulating layer. The array region includes a plurality of gate structures and a plurality of oxide layers alternately stacked on the P-type doped poly silicon layer, wherein a bottommost gate structure of the gate structures and the P-type doped poly silicon layer together serve as a plurality ground select lines of the semiconductor device. The array region further includes a vertical channel structure penetrating the gate structures and the oxide layers and extending into the N-type doped poly silicon layer.

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.