Abstract: A qubit assembly and a preparation method thereof, a quantum chip, and a chip preparation system are provided, which relate to the field of micro-nanofabrication technologies. The preparation method includes: preparing an underlying film of a qubit assembly on a substrate; preparing an underlying circuit based on the underlying film, a surface of the underlying circuit having a nitride passivation layer; and preparing, on the substrate, a qubit connected to the underlying circuit, to obtain the qubit assembly.

Abstract: This application relates to a photoresist removal method, including: acquiring a target wafer, a photoresist being provided on a surface of the target wafer, a surface of a photoresist layer of the photoresist being plated with a metal overhead layer; immersing the target wafer in a first organic solvent at a first temperature in a water bath for a first duration; rinsing the target wafer with a new first organic solvent in response to an end of the first duration; performing, in the first organic solvent, ultrasonic cleaning on the rinsed target wafer for a second duration based on a target ultrasonic power; removing the residual first organic solvent on the surface of the target wafer in response to an end of the second duration; and drying the target wafer with the solvent removed by simultaneous centrifugal drying and gas purging to obtain the target wafer with the photoresist removed.

Abstract: This application discloses methods and devices for a quantum chip, a quantum processor and a quantum computer, and relates to the field of quantum technology. The quantum chip includes a bottom sheet and a top sheet; a qubit array disposed on the top sheet, the qubit array comprising a plurality of qubits distributed in an array structure of M rows by N columns, and M and N being both integers greater than 1; a reading cavity disposed on the bottom sheet, and the reading cavity being configured to acquire status information of a qubit in the qubit array; and the bottom sheet and the top sheet being electrically connected.

Abstract: In a method for determining a superconducting impedance matched parametric amplifier, a center wavelength parameter, a gain parameter, and a bandwidth parameter of the superconducting impedance matched parametric amplifier are determined. An impedance value of an impedance matching line of the superconducting impedance matched parametric amplifier and a capacitance value of the amplifier are determined based on the wavelength parameter, the gain parameter, and the bandwidth parameter. A line width dimension of a coplanar waveguide of the superconducting impedance matched parametric amplifier is calculated based on the impedance value of the impedance matching line. A stub dimension of the superconducting impedance matched parametric amplifier is calculated based on the impedance value of the impedance matching line and the capacitance value of the amplifier.

Abstract: A chip preparation method and system, and a chip are provided. The method includes: preparing, by using a laser direct writing exposure manner, a first underlying circuit of an impedance Josephson parametric amplifier and a second underlying circuit for testing, to obtain a first chip product; generating, on the first chip product by using the laser direct writing exposure manner, a photoresist structure for preparing a Josephson junction; cutting, from the first chip product, a second chip product on which the second underlying circuit is located and a third chip product on which the first underlying circuit is located; preparing a Josephson junction sample based on a photoresist structure corresponding to the second underlying circuit, to obtain an oxidation condition; and preparing, according to the oxidation condition, the Josephson junction based on a photoresist structure corresponding to the first underlying circuit.

Abstract: This application provides a method for preparing a quantum chip. The method includes the following steps: determining an initial eigenfrequency of a chip substrate; performing, based on a numerical comparison result between the initial eigenfrequency and a quantum operating frequency, pattern etching on a first surface of the chip substrate to obtain a chip substrate with an intact second surface and the first surface with a target pattern, wherein the quantum operating frequency is an operating frequency of a quantum bit of a quantum circuit, the second surface is opposite to the first surface, and the target pattern is a pattern when a difference between the initial eigenfrequency of the chip substrate and the quantum operating frequency is maximum; and etching, on the second surface of the pattern-etched chip substrate, the quantum circuit to form the quantum chip.

Abstract: A method and system for preparing a Josephson junction is disclosed, relates to the technical field of micro-nano processing. The method includes: preparing a circuit structure on a substrate by nano-imprinting, the circuit structure comprising a first lead, a second lead, and a peripheral circuit connected to the first and second leads; preparing a photoresist-based undercut structure on the substrate; the undercut structure comprising a first region and a second region having upper photoresist layers and lower layers of hollow-out; the second region being an opening region of the undercut structure; preparing an oxide layer on a surface of the second lead which is not covered by the photoresist; evaporating a first superconducting layer obliquely in a direction from the first region to the second region to obtain the Josephson junction; and evaporating a second superconducting layer obliquely in a direction from the second region to the first region.

Abstract: A qubit assembly preparation method includes preparing a waveguide film in two or more regions on a substrate spaced apart from each other. The method further includes preparing, by using a Dolan bridge photoresist structure, a qubit structure not connected to the waveguide film. The qubit structure includes a three-layer structure. The three-layer structure includes a first superconducting portion and a second superconducting portion intersecting with each other in a coverage region on the substrate. The method further includes removing the insulation layer on a first target region and a second target region of an upper surface of the superconducting portion. The method further includes evaporating a connection layer on the waveguide film, the qubit structure, and the substrate between the waveguide film and the qubit structure.

Abstract: This application discloses a coating method for making a chip. The method includes: fixing a substrate on a base. The substrate includes a hole. The method includes controlling an included angle between a plane on which the substrate is located and a deposition direction of a coating material to be greater than 0 degrees and less than 90 degrees. The method includes controlling the substrate to rotate with respect to an axis perpendicular to the plane on which the substrate is located. The method includes during the rotation of the substrate, controlling the coating material to enter the hole along the deposition direction such that the coating material is deposited on a sidewall of the hole.

Abstract: This application relates to a photoresist removal method, including: acquiring a target wafer, a photoresist being provided on a surface of the target wafer, a surface of a photoresist layer of the photoresist being plated with a metal overhead layer; immersing the target wafer in a first organic solvent at a first temperature in a water bath for a first duration; rinsing the target wafer with a new first organic solvent in response to an end of the first duration; performing, in the first organic solvent, ultrasonic cleaning on the rinsed target wafer for a second duration based on a target ultrasonic power; removing the residual first organic solvent on the surface of the target wafer in response to an end of the second duration; and drying the target wafer with the solvent removed by simultaneous centrifugal drying and gas purging to obtain the target wafer with the photoresist removed.

Abstract: This application discloses methods and devices for a quantum chip, a quantum processor and a quantum computer, and relates to the field of quantum technology. The quantum chip includes a bottom sheet and a top sheet; a qubit array disposed on the top sheet, the qubit array comprising a plurality of qubits distributed in an array structure of M rows by N columns, and M and N being both integers greater than 1; a reading cavity disposed on the bottom sheet, and the reading cavity being configured to acquire status information of a qubit in the qubit array; and the bottom sheet and the top sheet being electrically connected.